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0526e7eaa9
common.cic unit is divided into common.cic.mon and common.cic.rm based on rm and mon process split. CIC-mon subunit includes the code which is utilized in critical interrupt handling path like initialization, error detection and error reporting path. CIC-rm subunit includes the code corresponding to rest of interrupt handling(like collecting error debug data from registers) and ISR status management (status of deferred interrupts). Split the CIC APIs and data-members into above two subunits. JIRA NVGPU-6899 Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
96 lines
3.0 KiB
C
96 lines
3.0 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/io.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_sgt.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/mc.h>
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#include "bus_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
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int gk20a_bus_init_hw(struct gk20a *g)
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{
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u32 intr_en_mask = 0U;
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nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
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/*
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* Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)
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* bus_intr_en_1 is for routing bus intr to nostall tree (mc_intr_1)
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*/
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if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
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intr_en_mask = bus_intr_en_1_pri_squash_m() |
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bus_intr_en_1_pri_fecserr_m() |
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bus_intr_en_1_pri_timeout_m();
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}
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nvgpu_writel(g, bus_intr_en_1_r(), intr_en_mask);
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if (g->ops.bus.configure_debug_bus != NULL) {
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g->ops.bus.configure_debug_bus(g);
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}
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return 0;
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}
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void gk20a_bus_isr(struct gk20a *g)
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{
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u32 val;
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u32 err_type = GPU_HOST_INVALID_ERROR;
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val = nvgpu_readl(g, bus_intr_0_r());
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if ((val & (bus_intr_0_pri_squash_m() |
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bus_intr_0_pri_fecserr_m() |
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bus_intr_0_pri_timeout_m())) != 0U) {
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if ((val & bus_intr_0_pri_squash_m()) != 0U) {
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err_type = GPU_HOST_PBUS_SQUASH_ERROR;
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}
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if ((val & bus_intr_0_pri_fecserr_m()) != 0U) {
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err_type = GPU_HOST_PBUS_FECS_ERROR;
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}
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if ((val & bus_intr_0_pri_timeout_m()) != 0U) {
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err_type = GPU_HOST_PBUS_TIMEOUT_ERROR;
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}
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g->ops.ptimer.isr(g);
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} else {
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nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val);
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/* We group following errors as part of PBUS_TIMEOUT_ERROR:
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* FB_REQ_TIMEOUT, FB_ACK_TIMEOUT, FB_ACK_EXTRA,
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* FB_RDATA_TIMEOUT, FB_RDATA_EXTRA, POSTED_DEADLOCK_TIMEOUT,
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* ACCESS_TIMEOUT.
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*/
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err_type = GPU_HOST_PBUS_TIMEOUT_ERROR;
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}
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nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
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0, err_type, val);
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nvgpu_writel(g, bus_intr_0_r(), val);
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}
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