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0526e7eaa9
common.cic unit is divided into common.cic.mon and common.cic.rm based on rm and mon process split. CIC-mon subunit includes the code which is utilized in critical interrupt handling path like initialization, error detection and error reporting path. CIC-rm subunit includes the code corresponding to rest of interrupt handling(like collecting error debug data from registers) and ISR status management (status of deferred interrupts). Split the CIC APIs and data-members into above two subunits. JIRA NVGPU-6899 Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
3.2 KiB
C
102 lines
3.2 KiB
C
/*
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/timers.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/gk20a.h>
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#include "bus_tu104.h"
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#include <nvgpu/hw/tu104/hw_bus_tu104.h>
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#include <nvgpu/hw/tu104/hw_func_tu104.h>
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int tu104_bus_init_hw(struct gk20a *g)
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{
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u32 intr_en_mask = 0U;
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nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
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/*
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* Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)
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* bus_intr_en_1 is for routing bus intr to nostall tree (mc_intr_1)
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*/
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if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
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intr_en_mask = bus_intr_en_0_pri_squash_m() |
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bus_intr_en_0_pri_fecserr_m() |
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bus_intr_en_0_pri_timeout_m();
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}
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nvgpu_writel(g, bus_intr_en_0_r(), intr_en_mask);
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if (g->ops.bus.configure_debug_bus != NULL) {
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g->ops.bus.configure_debug_bus(g);
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}
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return 0;
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}
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int bus_tu104_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst)
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{
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struct nvgpu_timeout timeout;
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int err = 0;
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u64 iova = nvgpu_inst_block_addr(g, bar2_inst);
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u32 ptr_v = (u32)(iova >> bus_bar2_block_ptr_shift_v());
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nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", ptr_v);
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err = nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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if (err != 0) {
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return err;
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}
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nvgpu_func_writel(g, func_priv_bar2_block_r(),
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nvgpu_aperture_mask(g, bar2_inst,
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bus_bar2_block_target_sys_mem_ncoh_f(),
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bus_bar2_block_target_sys_mem_coh_f(),
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bus_bar2_block_target_vid_mem_f()) |
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bus_bar2_block_mode_virtual_f() |
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bus_bar2_block_ptr_f(ptr_v));
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do {
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u32 val = nvgpu_func_readl(g,
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func_priv_bind_status_r());
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bool pending = (bus_bind_status_bar2_pending_v(val) ==
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bus_bind_status_bar2_pending_busy_v());
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bool outstanding = (bus_bind_status_bar2_outstanding_v(val) ==
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bus_bind_status_bar2_outstanding_true_v());
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if (!pending && !outstanding) {
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break;
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}
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nvgpu_udelay(5);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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if (nvgpu_timeout_peek_expired(&timeout)) {
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err = -EINVAL;
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}
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return err;
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}
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