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Add new hal g->ops.gr.init.commit_ctxsw_spill() in hal.gr.init unit to commit spill ctxsw buffer Define gp10b and gv11b operations Use new hals in gr_gp10b_update_ctxsw_preemption_mode() and gr_gv11b_update_ctxsw_preemption_mode() instead of directly committing using register accessors Jira NVGPU-2961 Change-Id: Iced02d304f12bcb4e78ea31a7728baa04081e325 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2084748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>