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0526e7eaa9
common.cic unit is divided into common.cic.mon and common.cic.rm based on rm and mon process split. CIC-mon subunit includes the code which is utilized in critical interrupt handling path like initialization, error detection and error reporting path. CIC-rm subunit includes the code corresponding to rest of interrupt handling(like collecting error debug data from registers) and ISR status management (status of deferred interrupts). Split the CIC APIs and data-members into above two subunits. JIRA NVGPU-6899 Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/nvgpu_err_info.h>
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#include <nvgpu/string.h>
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#include "cic_mon_priv.h"
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void nvgpu_init_err_msg_header(struct gpu_err_header *header)
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{
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header->version.major = (u16)1U;
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header->version.minor = (u16)0U;
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header->sub_err_type = 0U;
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header->sub_unit_id = 0UL;
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header->address = 0UL;
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header->timestamp_ns = 0UL;
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}
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void nvgpu_init_err_msg(struct nvgpu_err_msg *msg)
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{
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(void) memset(msg, 0, sizeof(struct nvgpu_err_msg));
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msg->hw_unit_id = 0U;
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msg->is_critical = false;
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msg->err_id = (u8)0U;
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msg->err_size = (u8)0U;
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}
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void nvgpu_init_host_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.host_info.header);
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}
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void nvgpu_init_ecc_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.ecc_info.header);
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msg->err_info.ecc_info.err_cnt = 0UL;
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}
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void nvgpu_init_pri_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.pri_info.header);
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}
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void nvgpu_init_ce_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.ce_info.header);
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}
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void nvgpu_init_pmu_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.pmu_err_info.header);
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msg->err_info.pmu_err_info.status = 0U;
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}
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void nvgpu_init_gr_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.gr_info.header);
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msg->err_info.gr_info.curr_ctx = 0U;
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msg->err_info.gr_info.chid = 0U;
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msg->err_info.gr_info.tsgid = 0U;
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msg->err_info.gr_info.status = 0U;
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}
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void nvgpu_init_ctxsw_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.ctxsw_info.header);
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msg->err_info.ctxsw_info.curr_ctx = 0U;
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msg->err_info.ctxsw_info.tsgid = 0U;
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msg->err_info.ctxsw_info.chid = 0U;
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msg->err_info.ctxsw_info.ctxsw_status0 = 0U;
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msg->err_info.ctxsw_info.ctxsw_status1 = 0U;
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msg->err_info.ctxsw_info.mailbox_value = 0U;
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}
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void nvgpu_init_mmu_err_msg(struct nvgpu_err_msg *msg)
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{
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nvgpu_init_err_msg(msg);
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nvgpu_init_err_msg_header(&msg->err_info.mmu_info.header);
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msg->err_info.mmu_info.info.inst_ptr = 0UL;
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msg->err_info.mmu_info.info.inst_aperture = 0U;
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msg->err_info.mmu_info.info.fault_addr = 0UL;
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msg->err_info.mmu_info.info.fault_addr_aperture = 0U;
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msg->err_info.mmu_info.info.timestamp_lo = 0U;
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msg->err_info.mmu_info.info.timestamp_hi = 0U;
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msg->err_info.mmu_info.info.mmu_engine_id = 0U;
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msg->err_info.mmu_info.info.gpc_id = 0U;
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msg->err_info.mmu_info.info.client_type = 0U;
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msg->err_info.mmu_info.info.client_id = 0U;
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msg->err_info.mmu_info.info.fault_type = 0U;
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msg->err_info.mmu_info.info.access_type = 0U;
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msg->err_info.mmu_info.info.protected_mode = 0U;
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msg->err_info.mmu_info.info.replayable_fault = false;
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msg->err_info.mmu_info.info.replay_fault_en = 0U;
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msg->err_info.mmu_info.info.valid = false;
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msg->err_info.mmu_info.info.faulted_pbdma = 0U;
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msg->err_info.mmu_info.info.faulted_engine = 0U;
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msg->err_info.mmu_info.info.faulted_subid = 0U;
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msg->err_info.mmu_info.info.chid = 0U;
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msg->err_info.mmu_info.status = 0U;
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}
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