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940cd280e1
- Assign base address for falcon based on falcon id. - Init mutex for falcon - Init ops with NULL Change-Id: I9efee5c2b15106c7dfc6e55c996f62c7f7b85fc2 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1468452 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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static void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
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{
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struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops;
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struct nvgpu_falcon_version_ops *flcn_vops = &flcn->flcn_vops;
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flcn_ops->reset = NULL;
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flcn_ops->enable_irq = NULL;
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flcn_ops->fbif_transcfg = NULL;
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flcn_ops->read_hwcfg = NULL;
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flcn_ops->write_hwcfg = NULL;
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flcn_ops->copy_from_dmem = NULL;
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flcn_ops->copy_to_dmem = NULL;
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flcn_ops->dma_copy = NULL;
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flcn_ops->mailbox_read = NULL;
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flcn_ops->mailbox_write = NULL;
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flcn_ops->get_unit_status = NULL;
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flcn_ops->dump_falcon_stats = NULL;
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flcn_vops->start_cpu_secure = NULL;
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flcn_vops->write_dmatrfbase = NULL;
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}
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void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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switch (flcn->flcn_id) {
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case FALCON_ID_PMU:
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flcn->flcn_base = FALCON_PWR_BASE;
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break;
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case FALCON_ID_SEC2:
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flcn->flcn_base = FALCON_SEC_BASE;
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break;
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case FALCON_ID_FECS:
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flcn->flcn_base = FALCON_FECS_BASE;
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break;
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case FALCON_ID_GPCCS:
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flcn->flcn_base = FALCON_GPCCS_BASE;
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break;
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default:
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nvgpu_err(g, "Invalid flcn request");
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break;
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}
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nvgpu_mutex_init(&flcn->copy_lock);
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gk20a_falcon_ops(flcn);
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}
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void gk20a_falcon_init_hal(struct gpu_ops *gops)
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{
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gops->falcon.falcon_hal_sw_init = gk20a_falcon_hal_sw_init;
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}
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