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7885500a42
Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
99 lines
3.3 KiB
C
99 lines
3.3 KiB
C
/*
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* Control pmgr state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _ctrlpmgr_h_
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#define _ctrlpmgr_h_
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#include "ctrlboardobj.h"
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/* valid power domain values */
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#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32
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#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06
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#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4E
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#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFF
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#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08
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#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30
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#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04
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#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0C
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#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8
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#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08
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#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFF
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#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFE
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#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFF)
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struct ctrl_pmgr_pwr_device_info_rshunt {
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bool use_fxp8_8;
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u16 rshunt_value;
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};
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struct ctrl_pmgr_pwr_policy_info_integral {
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u8 past_sample_count;
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u8 next_sample_count;
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u16 ratio_limit_min;
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u16 ratio_limit_max;
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};
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enum ctrl_pmgr_pwr_policy_filter_type {
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE = 0,
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK,
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE,
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR
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};
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struct ctrl_pmgr_pwr_policy_filter_param_block {
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u32 block_size;
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};
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struct ctrl_pmgr_pwr_policy_filter_param_moving_average {
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u32 window_size;
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};
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struct ctrl_pmgr_pwr_policy_filter_param_iir {
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u32 divisor;
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};
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union ctrl_pmgr_pwr_policy_filter_param {
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struct ctrl_pmgr_pwr_policy_filter_param_block block;
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struct ctrl_pmgr_pwr_policy_filter_param_moving_average moving_avg;
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struct ctrl_pmgr_pwr_policy_filter_param_iir iir;
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};
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struct ctrl_pmgr_pwr_policy_limit_input {
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u8 pwr_policy_idx;
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u32 limit_value;
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};
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struct ctrl_pmgr_pwr_policy_limit_arbitration {
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bool b_arb_max;
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u8 num_inputs;
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u32 output;
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struct ctrl_pmgr_pwr_policy_limit_input
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inputs[CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS];
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};
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#endif
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