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0e82e8d6c3
Move init_ce_engine_info from fifo to hal/engine unit as implementation is chip specific. Rename init_ce_engine_info to init_ce_info Rename gp10b_fifo_init_ce_engine_info to gp10b_engine_init_ce_info Rename gm20b_fifo_init_ce_engine_info to gm20b_engine_init_ce_info JIRA NVGPU-1313 Change-Id: Idb9ba3f2550eff6bbe7163d12e48086f47d3f319 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085427 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
/*
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* GM20B Fifo
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/timers.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/top.h>
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#include <nvgpu/engines.h>
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#include "gk20a/fifo_gk20a.h"
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#include "fifo_gm20b.h"
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void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch)
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{
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struct gk20a *g = ch->g;
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struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
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struct channel_gk20a *temp_ch;
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struct nvgpu_channel_hw_state hw_state;
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/* If CTX_RELOAD is set on a channel, move it to some other channel */
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g->ops.channel.read_state(g, ch, &hw_state);
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if (hw_state.ctx_reload) {
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nvgpu_rwsem_down_read(&tsg->ch_list_lock);
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nvgpu_list_for_each_entry(temp_ch, &tsg->ch_list, channel_gk20a, ch_entry) {
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if (temp_ch->chid != ch->chid) {
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g->ops.channel.force_ctx_reload(temp_ch);
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break;
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}
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}
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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}
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}
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