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gpu: nvgpu: move init_ce_engine_info from fifo to engine

Browse Source 
Move init_ce_engine_info from fifo to hal/engine unit as
implementation is chip specific.

Rename init_ce_engine_info to init_ce_info
Rename gp10b_fifo_init_ce_engine_info to gp10b_engine_init_ce_info
Rename gm20b_fifo_init_ce_engine_info to gm20b_engine_init_ce_info

JIRA NVGPU-1313

Change-Id: Idb9ba3f2550eff6bbe7163d12e48086f47d3f319
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085427
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-29 16:11:02 -07:00
committed by mobile promotions
parent ea1649ab6b
commit 0e82e8d6c3
16 changed files with 154 additions and 127 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile
View File

@@ -222,6 +222,7 @@ nvgpu-y += \
hal/fuse/fuse_gp10b.o \
hal/fuse/fuse_gp106.o \
hal/fifo/engines_gm20b.o \
hal/fifo/engines_gp10b.o \
hal/fifo/engines_gv11b.o \
hal/fifo/pbdma_gm20b.o \
hal/fifo/pbdma_gp10b.o \
@@ -508,7 +509,6 @@ nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \
nvgpu-y += \
gp10b/gr_gp10b.o \
gp10b/ce_gp10b.o \
gp10b/fifo_gp10b.o \
gp10b/mm_gp10b.o \
gp10b/hal_gp10b.o \
gp10b/gp10b.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -257,7 +257,6 @@ srcs += common/sim.c \
gm20b/mm_gm20b.c \
gp10b/gr_gp10b.c \
gp10b/ce_gp10b.c \
gp10b/fifo_gp10b.c \
gp10b/mm_gp10b.c \
gp10b/hal_gp10b.c \
gp10b/gp10b.c \
@@ -354,6 +353,7 @@ srcs += common/sim.c \
hal/fuse/fuse_gp10b.c \
hal/fuse/fuse_gp106.c \
hal/fifo/engines_gm20b.c \
hal/fifo/engines_gp10b.c \
hal/fifo/engines_gv11b.c \
hal/fifo/pbdma_gm20b.c \
hal/fifo/pbdma_gp10b.c \

2
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -793,7 +793,7 @@ int nvgpu_engine_init_info(struct fifo_gk20a *f)
dev_info.inst_id);
}
ret = g->ops.fifo.init_ce_engine_info(f);
ret = g->ops.engine.init_ce_info(f);
return ret;
}

93
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -38,10 +38,6 @@
#include "gk20a/fifo_gk20a.h"
#include "fifo_gm20b.h"
#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
#include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h>
void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch)
{
struct gk20a *g = ch->g;
@@ -62,92 +58,3 @@ void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch)
nvgpu_rwsem_up_read(&tsg->ch_list_lock);
}
}
int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
{
struct gk20a *g = f->g;
int ret = 0;
u32 i;
enum nvgpu_fifo_engine engine_enum;
u32 pbdma_id = U32_MAX;
u32 gr_runlist_id;
bool found_pbdma_for_runlist = false;
gr_runlist_id = nvgpu_engine_get_gr_runlist_id(g);
nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
if (g->ops.top.get_device_info != NULL) {
for (i = NVGPU_ENGINE_COPY0; i <= NVGPU_ENGINE_COPY2; i++) {
struct nvgpu_device_info dev_info;
struct fifo_engine_info_gk20a *info;
ret = g->ops.top.get_device_info(g, &dev_info, i, 0);
if (ret != 0) {
nvgpu_err(g,
"Failed to parse dev_info table for"
" engine %d", i);
return ret;
}
if (dev_info.engine_type != i) {
nvgpu_log_info(g, "No entry found in dev_info "
"table for engine_type %d", i);
continue;
}
found_pbdma_for_runlist =
g->ops.fifo.find_pbdma_for_runlist(f,
dev_info.runlist_id,
&pbdma_id);
if (!found_pbdma_for_runlist) {
nvgpu_err(g, "busted pbdma map");
return -EINVAL;
}
info = &g->fifo.engine_info[dev_info.engine_id];
engine_enum = nvgpu_engine_enum_from_type(g,
dev_info.engine_type);
/* GR and GR_COPY shares same runlist_id */
if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) &&
(gr_runlist_id == dev_info.runlist_id)) {
engine_enum = NVGPU_ENGINE_GRCE_GK20A;
}
info->engine_enum = engine_enum;
if (g->ops.top.get_ce_inst_id != NULL) {
dev_info.inst_id = g->ops.top.get_ce_inst_id(g,
dev_info.engine_type);
}
if ((dev_info.fault_id == 0U) &&
(engine_enum == NVGPU_ENGINE_GRCE_GK20A)) {
dev_info.fault_id = 0x1b;
}
info->fault_id = dev_info.fault_id;
info->intr_mask |= BIT32(dev_info.intr_id);
info->reset_mask |= BIT32(dev_info.reset_id);
info->runlist_id = dev_info.runlist_id;
info->pbdma_id = pbdma_id;
info->inst_id = dev_info.inst_id;
info->pri_base = dev_info.pri_base;
/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
f->active_engines_list[f->num_engines] =
dev_info.engine_id;
++f->num_engines;
nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
"intr_id %d reset_id %d engine_type %d "
"engine_enum %d inst_id %d",
dev_info.engine_id,
dev_info.runlist_id,
dev_info.intr_id,
dev_info.reset_id,
dev_info.engine_type,
engine_enum,
dev_info.inst_id);
}
}
return 0;
}

1
drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
View File

@@ -31,6 +31,5 @@ struct mmu_fault_info;
void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f);
#endif /* NVGPU_GM20B_FIFO_GM20B_H */

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -632,7 +632,6 @@ static const struct gpu_ops gm20b_ops = {
.set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask,
.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
.find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist,
.init_ce_engine_info = gm20b_fifo_init_ce_engine_info,
.intr_0_enable = gk20a_fifo_intr_0_enable,
.intr_1_enable = gk20a_fifo_intr_1_enable,
.intr_0_isr = gk20a_fifo_intr_0_isr,
@@ -651,6 +650,7 @@ static const struct gpu_ops gm20b_ops = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gm20b_engine_init_ce_info,
},
.pbdma = {
.intr_enable = gm20b_pbdma_intr_enable,

1
drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
View File

@@ -31,6 +31,5 @@ struct fifo_gk20a;
void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
u32 *inst_id, u32 *pri_base, u32 *fault_id);
void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f);
#endif

3
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -65,6 +65,7 @@
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
#include "hal/fifo/engines_gm20b.h"
#include "hal/fifo/engines_gp10b.h"
#include "hal/fifo/engine_status_gm20b.h"
#include "hal/fifo/pbdma_status_gm20b.h"
#include "hal/fifo/ramfc_gk20a.h"
@@ -720,7 +721,6 @@ static const struct gpu_ops gp10b_ops = {
.set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask,
.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
.find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist,
.init_ce_engine_info = gp10b_fifo_init_ce_engine_info,
.intr_0_enable = gk20a_fifo_intr_0_enable,
.intr_1_enable = gk20a_fifo_intr_1_enable,
.intr_0_isr = gk20a_fifo_intr_0_isr,
@@ -739,6 +739,7 @@ static const struct gpu_ops gp10b_ops = {
.is_fault_engine_subid_gpc = gm20b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {
.intr_enable = gm20b_pbdma_intr_enable,

3
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -53,6 +53,7 @@
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
#include "hal/fifo/pbdma_gv11b.h"
#include "hal/fifo/engines_gp10b.h"
#include "hal/fifo/engines_gv11b.h"
#include "hal/fifo/engine_status_gv100.h"
#include "hal/fifo/pbdma_status_gm20b.h"
@@ -904,7 +905,6 @@ static const struct gpu_ops gv100_ops = {
.doorbell_token = gv11b_fifo_doorbell_token,
.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
.find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist,
.init_ce_engine_info = gp10b_fifo_init_ce_engine_info,
.intr_0_enable = gk20a_fifo_intr_0_enable,
.intr_1_enable = gk20a_fifo_intr_1_enable,
.intr_0_isr = gv11b_fifo_intr_0_isr,
@@ -922,6 +922,7 @@ static const struct gpu_ops gv100_ops = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,

3
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -56,6 +56,7 @@
#include "hal/fifo/pbdma_gv11b.h"
#include "hal/fifo/engine_status_gv100.h"
#include "hal/fifo/pbdma_status_gm20b.h"
#include "hal/fifo/engines_gp10b.h"
#include "hal/fifo/engines_gv11b.h"
#include "hal/fifo/ramfc_gp10b.h"
#include "hal/fifo/ramfc_gv11b.h"
@@ -859,7 +860,6 @@ static const struct gpu_ops gv11b_ops = {
.doorbell_token = gv11b_fifo_doorbell_token,
.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
.find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist,
.init_ce_engine_info = gp10b_fifo_init_ce_engine_info,
.intr_0_enable = gv11b_fifo_intr_0_enable,
.intr_1_enable = gk20a_fifo_intr_1_enable,
.intr_0_isr = gv11b_fifo_intr_0_isr,
@@ -877,6 +877,7 @@ static const struct gpu_ops gv11b_ops = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,

97
drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c
View File

@@ -20,6 +20,12 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/top.h>
#include <nvgpu/engines.h>
#include <nvgpu/log.h>
#include <nvgpu/errno.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
#include "engines_gm20b.h"
@@ -28,3 +34,94 @@ bool gm20b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid)
{
return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v());
}
int gm20b_engine_init_ce_info(struct fifo_gk20a *f)
{
struct gk20a *g = f->g;
int ret = 0;
u32 i;
enum nvgpu_fifo_engine engine_enum;
u32 pbdma_id = U32_MAX;
u32 gr_runlist_id;
bool found_pbdma_for_runlist = false;
gr_runlist_id = nvgpu_engine_get_gr_runlist_id(g);
nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
if (g->ops.top.get_device_info != NULL) {
for (i = NVGPU_ENGINE_COPY0; i <= NVGPU_ENGINE_COPY2; i++) {
struct nvgpu_device_info dev_info;
struct fifo_engine_info_gk20a *info;
ret = g->ops.top.get_device_info(g, &dev_info, i, 0);
if (ret != 0) {
nvgpu_err(g,
"Failed to parse dev_info table for"
" engine %d", i);
return ret;
}
if (dev_info.engine_type != i) {
nvgpu_log_info(g, "No entry found in dev_info "
"table for engine_type %d", i);
continue;
}
found_pbdma_for_runlist =
g->ops.fifo.find_pbdma_for_runlist(f,
dev_info.runlist_id,
&pbdma_id);
if (!found_pbdma_for_runlist) {
nvgpu_err(g, "busted pbdma map");
return -EINVAL;
}
info = &g->fifo.engine_info[dev_info.engine_id];
engine_enum = nvgpu_engine_enum_from_type(g,
dev_info.engine_type);
/* GR and GR_COPY shares same runlist_id */
if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) &&
(gr_runlist_id ==
dev_info.runlist_id)) {
engine_enum = NVGPU_ENGINE_GRCE_GK20A;
}
info->engine_enum = engine_enum;
if (g->ops.top.get_ce_inst_id != NULL) {
dev_info.inst_id = g->ops.top.get_ce_inst_id(g,
dev_info.engine_type);
}
if ((dev_info.fault_id == 0U) &&
(engine_enum ==
NVGPU_ENGINE_GRCE_GK20A)) {
dev_info.fault_id = 0x1b;
}
info->fault_id = dev_info.fault_id;
info->intr_mask |= BIT32(dev_info.intr_id);
info->reset_mask |= BIT32(dev_info.reset_id);
info->runlist_id = dev_info.runlist_id;
info->pbdma_id = pbdma_id;
info->inst_id = dev_info.inst_id;
info->pri_base = dev_info.pri_base;
/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
f->active_engines_list[f->num_engines] =
dev_info.engine_id;
++f->num_engines;
nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
"intr_id %d reset_id %d engine_type %d "
"engine_enum %d inst_id %d",
dev_info.engine_id,
dev_info.runlist_id,
dev_info.intr_id,
dev_info.reset_id,
dev_info.engine_type,
engine_enum,
dev_info.inst_id);
}
}
return 0;
}

2
drivers/gpu/nvgpu/hal/fifo/engines_gm20b.h
View File

@@ -26,7 +26,9 @@
#include <nvgpu/types.h>
struct gk20a;
struct fifo_gk20a;
bool gm20b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid);
int gm20b_engine_init_ce_info(struct fifo_gk20a *f);
#endif /* NVGPU_ENGINE_GM20B_H */

33
drivers/gpu/nvgpu/gp10b/fifo_gp10b.c → drivers/gpu/nvgpu/hal/fifo/engines_gp10b.c
View File

@@ -1,6 +1,4 @@
/*
* GP10B fifo
*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -22,29 +20,17 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/dma.h>
#include <nvgpu/bug.h>
#include <nvgpu/log2.h>
#include <nvgpu/enabled.h>
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/channel.h>
#include <nvgpu/channel_sync.h>
#include <nvgpu/channel_sync_syncpt.h>
#include <nvgpu/engines.h>
#include <nvgpu/top.h>
#include <nvgpu/engines.h>
#include <nvgpu/log.h>
#include <nvgpu/errno.h>
#include <nvgpu/gk20a.h>
#include "fifo_gp10b.h"
#include "gk20a/fifo_gk20a.h"
#include "gm20b/fifo_gm20b.h"
#include <nvgpu/hw/gp10b/hw_pbdma_gp10b.h>
#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
#include "engines_gp10b.h"
int gp10b_engine_init_ce_info(struct fifo_gk20a *f)
{
struct gk20a *g = f->g;
int ret = 0;
@@ -93,8 +79,9 @@ int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
dev_info.engine_type);
/* GR and GR_COPY shares same runlist_id */
if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) &&
(gr_runlist_id == dev_info.runlist_id)) {
engine_enum = NVGPU_ENGINE_GRCE_GK20A;
(gr_runlist_id ==
dev_info.runlist_id)) {
engine_enum = NVGPU_ENGINE_GRCE_GK20A;
}
info->engine_enum = engine_enum;

32
drivers/gpu/nvgpu/hal/fifo/engines_gp10b.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_ENGINE_GP10B_H
#define NVGPU_ENGINE_GP10B_H
#include <nvgpu/types.h>
struct fifo_gk20a;
int gp10b_engine_init_ce_info(struct fifo_gk20a *f);
#endif /* NVGPU_ENGINE_GP10B_H */

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -981,7 +981,6 @@ struct gpu_ops {
u32 (*runlist_busy_engines)(struct gk20a *g, u32 runlist_id);
bool (*find_pbdma_for_runlist)(struct fifo_gk20a *f,
u32 runlist_id, u32 *pbdma_id);
int (*init_ce_engine_info)(struct fifo_gk20a *f);
struct {
int (*report_host_err)(struct gk20a *g,
u32 hw_id, u32 inst, u32 err_id,
@@ -1069,6 +1068,7 @@ struct gpu_ops {
u32 (*get_mask_on_id)(struct gk20a *g,
u32 id, bool is_tsg);
int (*init_info)(struct fifo_gk20a *f);
int (*init_ce_info)(struct fifo_gk20a *f);
} engine;
struct {

3
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -59,6 +59,7 @@
#include "hal/fifo/pbdma_gp10b.h"
#include "hal/fifo/pbdma_gv11b.h"
#include "hal/fifo/pbdma_tu104.h"
#include "hal/fifo/engines_gp10b.h"
#include "hal/fifo/engines_gv11b.h"
#include "hal/fifo/ramfc_gp10b.h"
#include "hal/fifo/ramfc_gv11b.h"
@@ -941,7 +942,6 @@ static const struct gpu_ops tu104_ops = {
.set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask,
.runlist_busy_engines = gk20a_fifo_runlist_busy_engines,
.find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist,
.init_ce_engine_info = gp10b_fifo_init_ce_engine_info,
.intr_0_enable = gv11b_fifo_intr_0_enable,
.intr_1_enable = gk20a_fifo_intr_1_enable,
.intr_0_isr = gv11b_fifo_intr_0_isr,
@@ -959,6 +959,7 @@ static const struct gpu_ops tu104_ops = {
.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
.get_mask_on_id = nvgpu_engine_get_mask_on_id,
.init_info = nvgpu_engine_init_info,
.init_ce_info = gp10b_engine_init_ce_info,
},
.pbdma = {
.intr_enable = gv11b_pbdma_intr_enable,