Vinod G c9caab84ad gpu: nvgpu: add new enable/disable hal for tpc_exception_sm bit ...

New tpc_exception_sm_disable hal to disable and
tpc_exception_sm_enable hal to enable the sm bit in tpc_exception
register.

These hals are added to avoid the register access in common gr code.

JIRA NVGPU-3016

Change-Id: I21634e2cd3b2b8007081e6f7608ec2da9c74813f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088311
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-04-04 12:34:57 -07:00

..

ce_gp10b.c

gpu: nvgpu: Enable the reporting of errors for CE

2019-03-01 09:54:21 -08:00

ce_gp10b.h

nvgpu: gp10b: MISRA Rule 21.2 header guard fixes

2018-09-24 21:17:51 -07:00

ecc_gp10b.c

gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>

2018-09-14 15:35:12 -07:00

ecc_gp10b.h

nvgpu: gp10b: MISRA Rule 21.2 header guard fixes

2018-09-24 21:17:51 -07:00

fifo_gp10b.h

gpu: nvgpu: move init_ce_engine_info from fifo to engine

2019-04-04 04:08:07 -07:00

gp10b.c

gpu: nvgpu: remove return value from init_gpu_characteristics

2019-01-30 16:44:26 -08:00

gp10b.h

gpu: nvgpu: remove return value from init_gpu_characteristics

2019-01-30 16:44:26 -08:00

gr_gp10b.c

gpu: nvgpu: add common.gr.obj_ctx apis to initialize/set preemption mode

2019-04-04 11:35:09 -07:00

gr_gp10b.h

gpu: nvgpu: add common.gr.obj_ctx apis to initialize/set preemption mode

2019-04-04 11:35:09 -07:00

hal_gp10b.c

gpu: nvgpu: add new enable/disable hal for tpc_exception_sm bit

2019-04-04 12:34:57 -07:00

hal_gp10b.h

gpu: nvgpu: Fix MISRA rule 8.3 violations

2018-11-12 22:33:18 -08:00

mm_gp10b.c

gpu: nvgpu: move init_pdb to ramin HAL

2019-04-03 09:55:23 -07:00

mm_gp10b.h

gpu: nvgpu: move init_pdb to ramin HAL

2019-04-03 09:55:23 -07:00