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5cde4c2140
Extract out the HAL ops' implementation that now belongs to the channel unit. This unit is responsible for channel register accesses and the like (ccsr_*). Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the rest of the naming. Same with channel_gv11b_unbind. Jira NVGPU-1307 Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
41 lines
1.7 KiB
C
41 lines
1.7 KiB
C
/*
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* GM20B Fifo
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_FIFO_GM20B_H
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#define NVGPU_GM20B_FIFO_GM20B_H
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struct gk20a;
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struct fifo_gk20a;
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struct mmu_fault_info;
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void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
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unsigned long engine_ids);
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void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
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void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault);
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int gm20b_fifo_init_engine_info(struct fifo_gk20a *f);
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int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f);
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#endif /* NVGPU_GM20B_FIFO_GM20B_H */
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