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Update the fifo code to use the HALs exposed by "Top" unit to read data from device_info table. The information for GRAPHICS engine in device_info table is now parsed using the get_device_info HAL from "Top" unit. Copy engine(CE) has multiple entries in the device_info table corresponding to each instance of the engine. Prior to Pascal, each instance of an engine was denoted by different engine type. For example in GM20B, there are engine types like COPY_ENGINE0, COPY_ENGINE1 and so on. In Pascal and chips beyond, a new field called "inst_id" is added and the engine_type is kept the same for different instances of an engine. For example in GP10B, all copy engine entries have same engine type i.e ENGINE_LCE, but different inst_ids. So for Pascal and chips beyond, we use a different HAL to get CE information from device_info table. JIRA NVGPU-1053 Change-Id: Ib40a616d903a5dbef5730678c2ebc3454b8e900d Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1969400 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
48 lines
2.0 KiB
C
48 lines
2.0 KiB
C
/*
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* GP10B Fifo
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_GP10B_H
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#define FIFO_GP10B_H
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struct gpu_ops;
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struct channel_gk20a;
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struct fifo_gk20a;
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struct mmu_fault_info;
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int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
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u64 gpfifo_base, u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags);
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u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g);
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int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c);
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void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
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u32 *inst_id, u32 *pri_base, u32 *fault_id);
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void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
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struct mmu_fault_info *mmfault);
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void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault);
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void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault);
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int channel_gp10b_commit_userd(struct channel_gk20a *c);
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int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f);
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#endif
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