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237cee5997
Extract out the HAL ops' implementation that now belongs to the runlist unit. Jira NVGPU-1309 Change-Id: I66185de0ddace1728da5f55ae11daa0b752bebf1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1997824 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
45 lines
1.9 KiB
C
45 lines
1.9 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FIFO_TU104_H
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#define NVGPU_FIFO_TU104_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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int channel_tu104_setup_ramfc(struct channel_gk20a *c,
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u64 gpfifo_base, u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags);
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int tu104_init_fifo_setup_hw(struct gk20a *g);
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void tu104_ring_channel_doorbell(struct channel_gk20a *c);
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u64 tu104_fifo_usermode_base(struct gk20a *g);
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u32 tu104_fifo_doorbell_token(struct channel_gk20a *c);
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int tu104_init_pdb_cache_war(struct gk20a *g);
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void tu104_deinit_pdb_cache_war(struct gk20a *g);
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u32 tu104_fifo_read_pbdma_data(struct gk20a *g, u32 pbdma_id);
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void tu104_fifo_reset_pbdma_header(struct gk20a *g, u32 pbdma_id);
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#endif /* NVGPU_FIFO_TU104_H */
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