mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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1d14a4412f
Add ioctls for creating, removing and querying scheduling domains and interface with the "nvsched" entity that will be the core scheduler. Include the scheduler in the Linux build. The core scheduler code will ultimately hold data on and control what gets scheduled, but this intermediate layer in nvgpu-rm needs a bit of bookeeping to manage the userspace interface. To keep changes isolated, this does not touch the internal runlist domains yet. The core scheduler logic will eventually control the runlist domains. Jira NVGPU-6788 Change-Id: I7b4064edb6205acbac2d8c593dad019d517243ce Signed-off-by: Alex Waterman <alexw@nvidia.com> Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2463625 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __NVGPU_IOCTL_H__
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#define __NVGPU_IOCTL_H__
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#include <linux/cdev.h>
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#include <nvgpu/types.h>
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#include <nvgpu/list.h>
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#include <nvgpu/mig.h>
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struct device;
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struct class;
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struct nvgpu_class {
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struct class *class;
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struct nvgpu_list_node list_entry;
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struct nvgpu_cdev_class_priv_data *priv_data;
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enum nvgpu_mig_gpu_instance_type instance_type;
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bool power_node;
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};
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static inline struct class *nvgpu_class_get_class(struct nvgpu_class *class)
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{
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return class->class;
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}
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struct nvgpu_cdev {
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struct cdev cdev;
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struct device *node;
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struct nvgpu_class *class;
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struct nvgpu_list_node list_entry;
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};
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static inline struct nvgpu_cdev *
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nvgpu_cdev_from_list_entry(struct nvgpu_list_node *node)
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{
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return (struct nvgpu_cdev *)
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((uintptr_t)node - offsetof(struct nvgpu_cdev, list_entry));
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};
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struct nvgpu_cdev_class_priv_data {
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char class_name[64];
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u32 local_instance_id;
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u32 major_instance_id;
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u32 minor_instance_id;
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bool pci;
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};
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static inline struct nvgpu_class *
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nvgpu_class_from_list_entry(struct nvgpu_list_node *node)
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{
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return (struct nvgpu_class *)
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((uintptr_t)node - offsetof(struct nvgpu_class, list_entry));
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};
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int gk20a_user_nodes_init(struct device *dev);
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int gk20a_power_node_init(struct device *dev);
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void gk20a_user_nodes_deinit(struct device *dev);
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void gk20a_power_node_deinit(struct device *dev);
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struct gk20a *nvgpu_get_gk20a_from_cdev(struct nvgpu_cdev *cdev);
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u32 nvgpu_get_gpu_instance_id_from_cdev(struct gk20a *g, struct nvgpu_cdev *cdev);
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#endif
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