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0e909daf1a
Add new unit common.gr.setup that provides runtime setup interfaces to other units outside of GR unit or to OS-specific code Move zcull setup call to this unit. New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup() Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove g->ops.gr.zcull.bind_ctxsw_zcull() Remove nvgpu_channel_gr_zcull_setup() from channel unit Also remove ctx/subctx header includes sicne channel code need not configure zcull Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common code Jira NVGPU-1886 Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2086602 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
81 lines
2.3 KiB
C
81 lines
2.3 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/gr/ctx.h>
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#include <nvgpu/gr/zcull.h>
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#include <nvgpu/gr/setup.h>
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#include <nvgpu/channel.h>
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static int nvgpu_gr_setup_zcull(struct gk20a *g, struct channel_gk20a *c,
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struct nvgpu_gr_ctx *gr_ctx)
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{
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int ret = 0;
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nvgpu_log_fn(g, " ");
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ret = gk20a_disable_channel_tsg(g, c);
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if (ret != 0) {
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nvgpu_err(g, "failed to disable channel/TSG");
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return ret;
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}
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ret = gk20a_fifo_preempt(g, c);
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if (ret != 0) {
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if (gk20a_enable_channel_tsg(g, c) != 0) {
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nvgpu_err(g, "failed to re-enable channel/TSG");
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}
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nvgpu_err(g, "failed to preempt channel/TSG");
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return ret;
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}
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ret = nvgpu_gr_zcull_ctx_setup(g, c->subctx, gr_ctx);
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if (ret != 0) {
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nvgpu_err(g, "failed to setup zcull");
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}
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ret = gk20a_enable_channel_tsg(g, c);
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if (ret != 0) {
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nvgpu_err(g, "failed to enable channel/TSG");
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}
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return ret;
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}
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int nvgpu_gr_setup_bind_ctxsw_zcull(struct gk20a *g, struct channel_gk20a *c,
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u64 zcull_va, u32 mode)
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{
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struct tsg_gk20a *tsg;
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struct nvgpu_gr_ctx *gr_ctx;
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tsg = tsg_gk20a_from_ch(c);
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if (tsg == NULL) {
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return -EINVAL;
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}
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gr_ctx = tsg->gr_ctx;
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nvgpu_gr_ctx_set_zcull_ctx(g, gr_ctx, mode, zcull_va);
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return nvgpu_gr_setup_zcull(g, c, gr_ctx);
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}
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