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11e29991ac
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the clk and clk_arb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I553353df836b187b8eac61e16b63080b570c96b8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1511076 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
88 lines
2.7 KiB
C
88 lines
2.7 KiB
C
/*
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* GM20B Graphics
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _NVHOST_CLK_GM20B_H_
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#define _NVHOST_CLK_GM20B_H_
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#include <nvgpu/lock.h>
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struct nvgpu_clk_pll_debug_data {
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u32 trim_sys_sel_vco_reg;
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u32 trim_sys_sel_vco_val;
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u32 trim_sys_gpc2clk_out_reg;
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u32 trim_sys_gpc2clk_out_val;
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u32 trim_sys_bypassctrl_reg;
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u32 trim_sys_bypassctrl_val;
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u32 trim_sys_gpcpll_cfg_reg;
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u32 trim_sys_gpcpll_dvfs2_reg;
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u32 trim_sys_gpcpll_cfg_val;
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bool trim_sys_gpcpll_cfg_enabled;
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bool trim_sys_gpcpll_cfg_locked;
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bool trim_sys_gpcpll_cfg_sync_on;
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u32 trim_sys_gpcpll_coeff_val;
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u32 trim_sys_gpcpll_coeff_mdiv;
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u32 trim_sys_gpcpll_coeff_ndiv;
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u32 trim_sys_gpcpll_coeff_pldiv;
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u32 trim_sys_gpcpll_dvfs0_val;
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u32 trim_sys_gpcpll_dvfs0_dfs_coeff;
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u32 trim_sys_gpcpll_dvfs0_dfs_det_max;
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u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset;
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};
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int gm20b_init_clk_setup_sw(struct gk20a *g);
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int gm20b_clk_prepare(struct clk_gk20a *clk);
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void gm20b_clk_unprepare(struct clk_gk20a *clk);
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int gm20b_clk_is_prepared(struct clk_gk20a *clk);
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unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate);
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int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate,
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unsigned long parent_rate);
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long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
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unsigned long *parent_rate);
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struct pll_parms *gm20b_get_gpc_pll_parms(void);
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#ifdef CONFIG_DEBUG_FS
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int gm20b_clk_init_debugfs(struct gk20a *g);
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#endif
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int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val);
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int gm20b_init_clk_support(struct gk20a *g);
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int gm20b_suspend_clk_support(struct gk20a *g);
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int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val);
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int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val);
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int gm20b_clk_get_pll_debug_data(struct gk20a *g,
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struct nvgpu_clk_pll_debug_data *d);
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/* 1:1 match between post divider settings and divisor value */
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static inline u32 nvgpu_pl_to_div(u32 pl)
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{
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return pl;
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}
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static inline u32 nvgpu_div_to_pl(u32 div)
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{
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return div;
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}
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#endif /* _NVHOST_CLK_GM20B_H_ */
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