mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 09:57:08 +03:00
90568a2ce5
This change solves two problems: (*) the possibility of a crash due to interrupting the gpu initialization following a bind (*) a IOVA memory leak that could prevent the GPU from binding after about 200 bind/unbind cycles A detailed list of fixes: - chek that arbiter is initialized before freeing it. - do not re-enable interrupts when MSI is enabled on unbind. - free the semaphore sea on unbind. - ensure we dont double load the vbios. - check return value of nvgpu_mutex_init for semaphores. - add corresponding nvgpu_mutex_destroy calls. bug 1816516 Change-Id: Ia8af73019e0e1183998855d55bb3eea09672a8b7 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1465302 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: David Jarrett <djarrett@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563019 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
257 lines
6.0 KiB
C
257 lines
6.0 KiB
C
/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/bios.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/enabled.h>
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#include "gk20a/gk20a.h"
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#include "gm20b/fifo_gm20b.h"
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#include "bios_gp106.h"
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#include "gp106/mclk_gp106.h"
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#ifdef CONFIG_DEBUG_FS
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#include "common/linux/os_linux.h"
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#endif
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#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
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#include <nvgpu/hw/gp106/hw_mc_gp106.h>
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#include <nvgpu/hw/gp106/hw_top_gp106.h>
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#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */
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#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */
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#define BIOS_OVERLAY_NAME "bios-%04x.rom"
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#define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom"
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#define ROM_FILE_PAYLOAD_OFFSET 0xa00
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#define BIOS_SIZE 0x40000
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static void upload_code(struct gk20a *g, u32 dst,
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u8 *src, u32 size, u8 port, bool sec)
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{
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nvgpu_flcn_copy_to_imem(g->pmu.flcn, dst, src, size, port, sec,
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dst >> 8);
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}
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static void upload_data(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port)
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{
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u32 i, words;
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u32 *src_u32 = (u32 *)src;
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u32 blk;
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gk20a_dbg_info("upload %d bytes to %x", size, dst);
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words = DIV_ROUND_UP(size, 4);
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blk = dst >> 8;
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gk20a_dbg_info("upload %d words to %x blk %d",
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words, dst, blk);
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gk20a_writel(g, pwr_falcon_dmemc_r(port),
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pwr_falcon_dmemc_offs_f(dst >> 2) |
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pwr_falcon_dmemc_blk_f(blk) |
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pwr_falcon_dmemc_aincw_f(1));
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for (i = 0; i < words; i++)
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gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]);
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}
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static int gp106_bios_devinit(struct gk20a *g)
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{
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int err = 0;
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int devinit_completed;
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struct nvgpu_timeout timeout;
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gk20a_dbg_fn("");
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if (nvgpu_flcn_reset(g->pmu.flcn)) {
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err = -ETIMEDOUT;
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goto out;
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}
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upload_code(g, g->bios.devinit.bootloader_phys_base,
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g->bios.devinit.bootloader,
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g->bios.devinit.bootloader_size,
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0, 0);
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upload_code(g, g->bios.devinit.phys_base,
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g->bios.devinit.ucode,
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g->bios.devinit.size,
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0, 1);
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upload_data(g, g->bios.devinit.dmem_phys_base,
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g->bios.devinit.dmem,
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g->bios.devinit.dmem_size,
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0);
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upload_data(g, g->bios.devinit_tables_phys_base,
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g->bios.devinit_tables,
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g->bios.devinit_tables_size,
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0);
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upload_data(g, g->bios.devinit_script_phys_base,
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g->bios.bootscripts,
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g->bios.bootscripts_size,
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0);
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nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point);
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nvgpu_timeout_init(g, &timeout,
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PMU_BOOT_TIMEOUT_MAX /
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PMU_BOOT_TIMEOUT_DEFAULT,
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NVGPU_TIMER_RETRY_TIMER);
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do {
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devinit_completed = pwr_falcon_cpuctl_halt_intr_v(
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gk20a_readl(g, pwr_falcon_cpuctl_r())) &&
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top_scratch1_devinit_completed_v(
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gk20a_readl(g, top_scratch1_r()));
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nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
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} while (!devinit_completed && !nvgpu_timeout_expired(&timeout));
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if (nvgpu_timeout_peek_expired(&timeout))
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err = -ETIMEDOUT;
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nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn,
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gk20a_get_gr_idle_timeout(g));
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out:
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gk20a_dbg_fn("done");
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return err;
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}
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static int gp106_bios_preos(struct gk20a *g)
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{
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int err = 0;
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gk20a_dbg_fn("");
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if (nvgpu_flcn_reset(g->pmu.flcn)) {
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err = -ETIMEDOUT;
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goto out;
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}
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upload_code(g, g->bios.preos.bootloader_phys_base,
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g->bios.preos.bootloader,
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g->bios.preos.bootloader_size,
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0, 0);
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upload_code(g, g->bios.preos.phys_base,
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g->bios.preos.ucode,
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g->bios.preos.size,
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0, 1);
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upload_data(g, g->bios.preos.dmem_phys_base,
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g->bios.preos.dmem,
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g->bios.preos.dmem_size,
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0);
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nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point);
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if (nvgpu_flcn_wait_for_halt(g->pmu.flcn,
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PMU_BOOT_TIMEOUT_MAX / 1000)) {
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err = -ETIMEDOUT;
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goto out;
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}
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nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn,
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gk20a_get_gr_idle_timeout(g));
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out:
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gk20a_dbg_fn("done");
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return err;
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}
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int gp106_bios_init(struct gk20a *g)
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{
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unsigned int i;
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#ifdef CONFIG_DEBUG_FS
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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struct dentry *d;
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#endif
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int err;
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gk20a_dbg_fn("");
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if (g->bios_is_init)
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return 0;
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gk20a_dbg_info("reading bios from EEPROM");
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g->bios.size = BIOS_SIZE;
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g->bios.data = nvgpu_vmalloc(g, BIOS_SIZE);
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if (!g->bios.data)
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return -ENOMEM;
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g->ops.xve.disable_shadow_rom(g);
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for (i = 0; i < g->bios.size/4; i++) {
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u32 val = be32_to_cpu(gk20a_readl(g, 0x300000 + i*4));
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g->bios.data[(i*4)] = (val >> 24) & 0xff;
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g->bios.data[(i*4)+1] = (val >> 16) & 0xff;
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g->bios.data[(i*4)+2] = (val >> 8) & 0xff;
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g->bios.data[(i*4)+3] = val & 0xff;
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}
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g->ops.xve.enable_shadow_rom(g);
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err = nvgpu_bios_parse_rom(g);
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if (err)
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goto free_firmware;
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if (g->gpu_characteristics.vbios_version < g->vbios_min_version) {
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nvgpu_err(g, "unsupported VBIOS version %08x",
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g->gpu_characteristics.vbios_version);
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err = -EINVAL;
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goto free_firmware;
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}
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/* WAR for HW2.5 RevA (INA3221 is missing) */
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if ((g->pci_vendor_id == PCI_VENDOR_ID_NVIDIA) &&
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(g->pci_device_id == 0x1c75) &&
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(g->gpu_characteristics.vbios_version == 0x86065300)) {
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g->power_sensor_missing = true;
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}
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#ifdef CONFIG_DEBUG_FS
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g->bios_blob.data = g->bios.data;
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g->bios_blob.size = g->bios.size;
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d = debugfs_create_blob("bios", S_IRUGO, l->debugfs,
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&g->bios_blob);
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if (!d) {
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err = -EINVAL;
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nvgpu_err(g, "No debugfs?");
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goto free_firmware;
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}
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#endif
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gk20a_dbg_fn("done");
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err = gp106_bios_devinit(g);
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if (err) {
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nvgpu_err(g, "devinit failed");
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goto free_debugfs;
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}
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if (nvgpu_is_enabled(g, NVGPU_PMU_RUN_PREOS)) {
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err = gp106_bios_preos(g);
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if (err) {
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nvgpu_err(g, "pre-os failed");
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goto free_debugfs;
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}
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}
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g->bios_is_init = true;
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return 0;
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free_debugfs:
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#ifdef CONFIG_DEBUG_FS
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debugfs_remove(d);
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#endif
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free_firmware:
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if (g->bios.data)
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nvgpu_vfree(g, g->bios.data);
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return err;
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}
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