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11e29991ac
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the clk and clk_arb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I553353df836b187b8eac61e16b63080b570c96b8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1511076 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "clk/clk_arb.h"
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#include "clk_arb_gp106.h"
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u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
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{
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(void)g;
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return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
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}
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int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz)
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{
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enum nv_pmu_clk_clkwhich clkwhich;
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struct clk_set_info *p0_info;
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struct clk_set_info *p5_info;
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struct avfsfllobjs *pfllobjs = &(g->clk_pmu.avfs_fllobjs);
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u16 limit_min_mhz;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_MCLK:
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clkwhich = clkwhich_mclk;
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break;
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case CTRL_CLK_DOMAIN_GPC2CLK:
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clkwhich = clkwhich_gpc2clk;
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break;
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default:
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return -EINVAL;
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}
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p5_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P5, clkwhich);
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if (!p5_info)
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return -EINVAL;
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p0_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P0, clkwhich);
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if (!p0_info)
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return -EINVAL;
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limit_min_mhz = p5_info->min_mhz;
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/* WAR for DVCO min */
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if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK)
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if ((pfllobjs->max_min_freq_mhz) &&
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(pfllobjs->max_min_freq_mhz > limit_min_mhz))
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limit_min_mhz = pfllobjs->max_min_freq_mhz;
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*min_mhz = limit_min_mhz;
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*max_mhz = p0_info->max_mhz;
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return 0;
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}
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int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
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u16 *default_mhz)
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{
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enum nv_pmu_clk_clkwhich clkwhich;
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struct clk_set_info *p0_info;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_MCLK:
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clkwhich = clkwhich_mclk;
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break;
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case CTRL_CLK_DOMAIN_GPC2CLK:
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clkwhich = clkwhich_gpc2clk;
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break;
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default:
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return -EINVAL;
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}
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p0_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P0, clkwhich);
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if (!p0_info)
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return -EINVAL;
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*default_mhz = p0_info->max_mhz;
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return 0;
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}
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