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11e29991ac
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the clk and clk_arb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I553353df836b187b8eac61e16b63080b570c96b8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1511076 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CLK_GP106_H
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#define CLK_GP106_H
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#include <nvgpu/lock.h>
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#define CLK_NAMEMAP_INDEX_GPC2CLK 0x00
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#define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02
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#define CLK_NAMEMAP_INDEX_SYS2CLK 0x07 /* SYSPLL */
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#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
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#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
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#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
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#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
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#define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */
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#define XTAL_SCALE_TO_KHZ 1
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struct namemap_cfg {
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u32 namemap;
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u32 is_enable; /* Namemap enabled */
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u32 is_counter; /* Using cntr */
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struct gk20a *g;
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union {
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struct {
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u32 reg_ctrl_addr;
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u32 reg_ctrl_idx;
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u32 reg_cntr_addr;
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} cntr;
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struct {
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/* Todo */
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} pll;
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};
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u32 scale;
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char name[24];
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};
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int gp106_init_clk_support(struct gk20a *g);
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u32 gp106_crystal_clk_hz(struct gk20a *g);
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unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain);
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int gp106_suspend_clk_support(struct gk20a *g);
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#endif /* CLK_GP106_H */
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