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b117f40f6c
tegra_fuse_readl is supported in upstream. Separate out the functions using this API from the config CONFIG_NVGPU_TEGRA_FUSE. Following four fuses are defined in downstream kernel repositories in tegra fuse header. It can be incorporated in upstream if nvgpu starts reading those fuses using nvmem APIs. Hence define those fuse offsets in nvgpu itself for now. 1. FUSE_RESERVED_CALIB0_0 2. FUSE_GCPLEX_CONFIG_FUSE_0 3. FUSE_PDI0 4. FUSE_PDI1 Bug 200625647 Change-Id: I8da8c0c3a0682fdab806fa57035fedd29ef22c26 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2369955 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/fuse.h>
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#include <nvgpu/linux/soc_fuse.h>
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#include <soc/tegra/fuse.h>
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int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
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{
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*id = tegra_sku_info.gpu_speedo_id;
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return 0;
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}
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int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
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}
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int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
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}
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int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
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{
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u32 lo = 0U;
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u32 hi = 0U;
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int err;
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err = tegra_fuse_readl(FUSE_PDI0, &lo);
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if (err)
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return err;
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err = tegra_fuse_readl(FUSE_PDI1, &hi);
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if (err)
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return err;
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*pdi = ((u64)lo) | (((u64)hi) << 32);
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return 0;
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}
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#ifdef CONFIG_NVGPU_TEGRA_FUSE
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/*
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* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
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* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
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*/
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void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
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{
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tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
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}
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void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
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{
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tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
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}
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#endif /* CONFIG_NVGPU_TEGRA_FUSE */
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