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6c6aab952e
The submit gpfifo flags are splattered everywhere inside the nvgpu code. Though the usage is inside nvgpu Linux code only, still it needs to be gotten rid of and replaced with the defines present in common code. VQRM-3465 Change-Id: I901b33565b01fa3e1f9ba6698a323c16547a8d3e Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691979 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVGPU_CHANNEL_H__
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#define __NVGPU_CHANNEL_H__
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#include <linux/workqueue.h>
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#include <linux/dma-buf.h>
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#include <nvgpu/types.h>
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struct channel_gk20a;
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struct nvgpu_gpfifo;
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struct nvgpu_submit_gpfifo_args;
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struct nvgpu_channel_fence;
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struct gk20a_fence;
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struct fifo_profile_gk20a;
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struct nvgpu_os_linux;
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struct nvgpu_channel_completion_cb {
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/*
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* Signal channel owner via a callback, if set, in job cleanup with
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* schedule_work. Means that something finished on the channel (perhaps
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* more than one job).
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*/
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void (*fn)(struct channel_gk20a *, void *);
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void *user_data;
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/* Make access to the two above atomic */
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struct nvgpu_spinlock lock;
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/* Per-channel async work task, cannot reschedule itself */
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struct work_struct work;
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};
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struct nvgpu_error_notifier {
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struct dma_buf *dmabuf;
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void *vaddr;
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struct nvgpu_notification *notification;
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struct nvgpu_mutex mutex;
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};
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struct nvgpu_channel_linux {
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struct channel_gk20a *ch;
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struct nvgpu_channel_completion_cb completion_cb;
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struct nvgpu_error_notifier error_notifier;
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struct dma_buf *cyclestate_buffer_handler;
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};
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u32 nvgpu_submit_gpfifo_user_flags_to_common_flags(u32 user_flags);
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int nvgpu_init_channel_support_linux(struct nvgpu_os_linux *l);
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void nvgpu_remove_channel_support_linux(struct nvgpu_os_linux *l);
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struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g,
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void (*update_fn)(struct channel_gk20a *, void *),
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void *update_fn_data,
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int runlist_id,
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bool is_privileged_channel);
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int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
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struct nvgpu_gpfifo_entry *gpfifo,
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struct nvgpu_submit_gpfifo_args *args,
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u32 num_entries,
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u32 flags,
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struct nvgpu_channel_fence *fence,
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struct gk20a_fence **fence_out,
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bool force_need_sync_fence,
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struct fifo_profile_gk20a *profile);
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#endif /* __NVGPU_CHANNEL_H__ */
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