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9355345610
When GPU need to programmed with PA(physical address), given IPA need to be converted to PA by querying Hypervisor. As this is an IPC between OSes, the call will reduce the performance badly. So this is adding a IPA-PA cache to improve the performance. This will be more helpful in passthr config. Bug 3277194 Change-Id: I6a3230d858977313a0ed0f33068055a3b516330a Signed-off-by: dt <dt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2571814 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/version.h>
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)
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#include <soc/tegra/chip-id.h>
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#endif
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#include <soc/tegra/fuse.h>
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#ifdef CONFIG_TEGRA_HV_MANAGER
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#include <soc/tegra/virt/syscalls.h>
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#include <nvgpu/ipa_pa_cache.h>
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#endif
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#include <nvgpu/soc.h>
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#include "os_linux.h"
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#include "platform_gk20a.h"
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bool nvgpu_platform_is_silicon(struct gk20a *g)
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{
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return tegra_platform_is_silicon();
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}
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bool nvgpu_platform_is_simulation(struct gk20a *g)
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{
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return tegra_platform_is_vdk();
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}
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bool nvgpu_platform_is_fpga(struct gk20a *g)
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{
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return tegra_platform_is_fpga();
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}
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bool nvgpu_is_hypervisor_mode(struct gk20a *g)
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{
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return is_tegra_hypervisor_mode();
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}
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bool nvgpu_is_soc_t194_a01(struct gk20a *g)
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{
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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return ((platform->platform_chip_id == TEGRA_194 &&
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tegra_chip_get_revision() == TEGRA_REVISION_A01) ?
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true : false);
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}
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#ifdef CONFIG_TEGRA_HV_MANAGER
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/* When nvlink is enabled on dGPU, we need to use physical memory addresses.
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* There is no SMMU translation. However, the device initially enumerates as a
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* PCIe device. As such, when allocation memory for this PCIe device, the DMA
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* framework ends up allocating memory using SMMU (if enabled in device tree).
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* As a result, when we switch to nvlink, we need to use underlying physical
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* addresses, even if memory mappings exist in SMMU.
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* In addition, when stage-2 SMMU translation is enabled (for instance when HV
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* is enabled), the addresses we get from dma_alloc are IPAs. We need to
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* convert them to PA.
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*/
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static u64 nvgpu_tegra_hv_ipa_pa(struct gk20a *g, u64 ipa, u64 *pa_len)
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{
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct hyp_ipa_pa_info info;
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int err;
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u64 pa = 0ULL;
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pa = nvgpu_ipa_to_pa_cache_lookup_locked(g, ipa, pa_len);
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if (pa != 0UL) {
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return pa;
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}
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err = hyp_read_ipa_pa_info(&info, platform->vmid, ipa);
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if (err < 0) {
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nvgpu_err(g, "ipa=%llx translation failed vmid=%u err=%d",
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ipa, platform->vmid, err);
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} else {
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pa = info.base + info.offset;
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if (pa_len != NULL) {
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/*
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* Update the size of physical memory chunk after the
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* specified offset.
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*/
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*pa_len = info.size - info.offset;
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}
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nvgpu_log(g, gpu_dbg_map_v,
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"ipa=%llx vmid=%d -> pa=%llx "
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"base=%llx offset=%llx size=%llx\n",
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ipa, platform->vmid, pa, info.base,
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info.offset, info.size);
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}
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if (pa != 0U) {
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nvgpu_ipa_to_pa_add_to_cache(g, ipa, pa, &info);
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}
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return pa;
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}
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#endif
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int nvgpu_init_soc_vars(struct gk20a *g)
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{
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#ifdef CONFIG_TEGRA_HV_MANAGER
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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int err;
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if (nvgpu_is_hypervisor_mode(g)) {
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err = hyp_read_gid(&platform->vmid);
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if (err) {
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nvgpu_err(g, "failed to read vmid");
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return err;
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}
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platform->phys_addr = nvgpu_tegra_hv_ipa_pa;
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}
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#endif
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return 0;
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}
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