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bb677160e5
In gk20a_gr_handle_fecs_error(), we right now check the error code in mailbox to identify if we hit timestamp buffer full error interrupt This error code right now is hard coded to 0x26 But on Turing ucode this error code is set to 0x32 Add new HAL g->ops.fecs_trace.get_buffer_full_mailbox_val() to get correct error code per platform and use this in gk20a_gr_handle_fecs_error() Bug 200471541 Bug 2469604 Change-Id: I7325354b39d35b1c8b218e554814316d22950469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1978144 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
48 lines
2.1 KiB
C
48 lines
2.1 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GK20A_FECS_TRACE_GK20A_H
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#define NVGPU_GK20A_FECS_TRACE_GK20A_H
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struct gk20a;
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struct channel_gk20a;
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struct nvgpu_gpu_ctxsw_trace_filter;
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struct nvgpu_gr_ctx;
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int gk20a_fecs_trace_poll(struct gk20a *g);
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int gk20a_fecs_trace_init(struct gk20a *g);
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int gk20a_fecs_trace_bind_channel(struct gk20a *g,
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struct channel_gk20a *ch, struct nvgpu_gr_ctx *gr_ctx);
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int gk20a_fecs_trace_unbind_channel(struct gk20a *g, struct channel_gk20a *ch);
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int gk20a_fecs_trace_reset(struct gk20a *g);
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int gk20a_fecs_trace_deinit(struct gk20a *g);
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int gk20a_gr_max_entries(struct gk20a *g,
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struct nvgpu_gpu_ctxsw_trace_filter *filter);
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int gk20a_fecs_trace_enable(struct gk20a *g);
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int gk20a_fecs_trace_disable(struct gk20a *g);
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bool gk20a_fecs_trace_is_enabled(struct gk20a *g);
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size_t gk20a_fecs_trace_buffer_size(struct gk20a *g);
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void gk20a_fecs_trace_reset_buffer(struct gk20a *g);
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u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void);
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#endif /* NVGPU_GK20A_FECS_TRACE_GK20A_H */
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