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gpu: nvgpu: check tu104 specific timestamp buffer full error code

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In gk20a_gr_handle_fecs_error(), we right now check the error code in
mailbox to identify if we hit timestamp buffer full error interrupt
This error code right now is hard coded to 0x26

But on Turing ucode this error code is set to 0x32

Add new HAL g->ops.fecs_trace.get_buffer_full_mailbox_val() to get
correct error code per platform and use this in
gk20a_gr_handle_fecs_error()

Bug 200471541
Bug 2469604

Change-Id: I7325354b39d35b1c8b218e554814316d22950469
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978144
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-12-21 19:32:25 +05:30
committed by mobile promotions
parent 8a55a6066d
commit bb677160e5
14 changed files with 97 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/Makefile
View File

@@ -297,6 +297,9 @@ nvgpu-y += \
gm20b/mm_gm20b.o \
gm20b/regops_gm20b.o
nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \
tu104/fecs_trace_tu104.o \
nvgpu-$(CONFIG_GK20A_VIDMEM) += \
common/mm/vidmem.o

5
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
View File

@@ -603,4 +603,9 @@ void gk20a_fecs_trace_reset_buffer(struct gk20a *g)
gk20a_fecs_trace_set_read_index(g,
gk20a_fecs_trace_get_write_index(g));
}
u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void)
{
return 0x26;
}
#endif /* CONFIG_GK20A_CTXSW_TRACE */

1
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
View File

@@ -42,5 +42,6 @@ int gk20a_fecs_trace_disable(struct gk20a *g);
bool gk20a_fecs_trace_is_enabled(struct gk20a *g);
size_t gk20a_fecs_trace_buffer_size(struct gk20a *g);
void gk20a_fecs_trace_reset_buffer(struct gk20a *g);
u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void);
#endif /* NVGPU_GK20A_FECS_TRACE_GK20A_H */

20
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5064,23 +5064,27 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
"cannot ctxsw anymore !!", chid);
g->ops.gr.dump_gr_falcon_stats(g);
} else if ((gr_fecs_intr &
gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
if (mailbox_value == MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL) {
#ifdef CONFIG_GK20A_CTXSW_TRACE
if (mailbox_value ==
g->ops.fecs_trace.get_buffer_full_mailbox_val()) {
nvgpu_info(g, "ctxsw intr0 set by ucode, "
"timestamp buffer full");
#ifdef CONFIG_GK20A_CTXSW_TRACE
gk20a_fecs_trace_reset_buffer(g);
#else
ret = -1;
#endif
} else {
nvgpu_err(g,
"ctxsw intr0 set by ucode, error_code: 0x%08x",
mailbox_value);
"ctxsw intr0 set by ucode, error_code: 0x%08x",
mailbox_value);
ret = -1;
}
#else
nvgpu_err(g,
"ctxsw intr0 set by ucode, error_code: 0x%08x",
mailbox_value);
ret = -1;
#endif
} else {
nvgpu_err(g,
"unhandled fecs error interrupt 0x%08x for channel %u",

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -69,8 +69,6 @@
#define CTXSW_INTR0 BIT32(0)
#define CTXSW_INTR1 BIT32(1)
#define MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x26
struct tsg_gk20a;
struct channel_gk20a;
struct nvgpu_warpstate;

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -630,6 +630,8 @@ static const struct gpu_ops gp10b_ops = {
.bind_channel = gk20a_fecs_trace_bind_channel,
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = gk20a_gr_max_entries,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -805,6 +805,8 @@ static const struct gpu_ops gv100_ops = {
.bind_channel = gk20a_fecs_trace_bind_channel,
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = gk20a_gr_max_entries,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -759,6 +759,8 @@ static const struct gpu_ops gv11b_ops = {
.bind_channel = gk20a_fecs_trace_bind_channel,
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = gk20a_gr_max_entries,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1039,6 +1039,7 @@ struct gpu_ops {
struct vm_area_struct *vma);
int (*set_filter)(struct gk20a *g,
struct nvgpu_gpu_ctxsw_trace_filter *filter);
u32 (*get_buffer_full_mailbox_val)(void);
} fecs_trace;
#endif
struct {

28
drivers/gpu/nvgpu/tu104/fecs_trace_tu104.c Normal file
View File

@@ -0,0 +1,28 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "fecs_trace_tu104.h"
u32 tu104_fecs_trace_get_buffer_full_mailbox_val(void)
{
return 0x32;
}

30
drivers/gpu/nvgpu/tu104/fecs_trace_tu104.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FECS_TRACE_TU104_H
#define NVGPU_FECS_TRACE_TU104_H
#include <nvgpu/types.h>
u32 tu104_fecs_trace_get_buffer_full_mailbox_val(void);
#endif /* NVGPU_FECS_TRACE_TU104_H */

3
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -125,6 +125,7 @@
#include "tu104/ecc_tu104.h"
#include "tu104/hal_tu104.h"
#include "tu104/regops_tu104.h"
#include "tu104/fecs_trace_tu104.h"
#include <nvgpu/ptimer.h>
#include <nvgpu/debug.h>
@@ -835,6 +836,8 @@ static const struct gpu_ops tu104_ops = {
.bind_channel = gk20a_fecs_trace_bind_channel,
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = gk20a_gr_max_entries,
.get_buffer_full_mailbox_val =
tu104_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

4
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -64,6 +64,8 @@
#include "gm20b/fifo_gm20b.h"
#include "gm20b/mm_gm20b.h"
#include "gk20a/fecs_trace_gk20a.h"
#include <nvgpu/debugger.h>
#include <nvgpu/enabled.h>
#include <nvgpu/vgpu/vgpu.h>
@@ -451,6 +453,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.unbind_channel = NULL,
.max_entries = vgpu_fecs_trace_max_entries,
.set_filter = vgpu_fecs_trace_set_filter,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

4
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -77,6 +77,8 @@
#include <gv100/gr_gv100.h>
#include "gk20a/fecs_trace_gk20a.h"
#include <nvgpu/debugger.h>
#include <nvgpu/enabled.h>
#include <nvgpu/channel.h>
@@ -529,6 +531,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.unbind_channel = NULL,
.max_entries = vgpu_fecs_trace_max_entries,
.set_filter = vgpu_fecs_trace_set_filter,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {