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0158c38037
Fix sparse warnings of below type by making necessary symbols static: warning: symbol '<symbol>' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
/*
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* GK20A Graphics Copy Engine (gr host)
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*
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* Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
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#include "hw_ce2_gp10b.h"
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#include "ce2_gp10b.h"
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static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
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/* wake theads waiting in this channel */
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gk20a_channel_semaphore_wakeup(g);
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return ce2_intr_status_nonblockpipe_pending_f();
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}
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static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
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return ce2_intr_status_blockpipe_pending_f();
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}
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static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n");
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return ce2_intr_status_launcherr_pending_f();
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}
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static void gp10b_ce2_isr(struct gk20a *g)
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{
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u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
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u32 clear_intr = 0;
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gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
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/* clear blocking interrupts: they exibit broken behavior */
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if (ce2_intr & ce2_intr_status_blockpipe_pending_f())
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clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
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if (ce2_intr & ce2_intr_status_launcherr_pending_f())
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clear_intr |= ce2_launcherr_isr(g, ce2_intr);
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gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
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return;
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}
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static void gp10b_ce2_nonstall_isr(struct gk20a *g)
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{
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u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
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u32 clear_intr = 0;
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gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
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if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f())
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clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr);
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gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
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return;
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}
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void gp10b_init_ce2(struct gpu_ops *gops)
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{
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gops->ce2.isr_stall = gp10b_ce2_isr;
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gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr;
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}
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