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4493b6b200
Allow enabling CILP for compute. Set CTA by default. Bug 1517461 Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661298 GVS: Gerrit_Virtual_Submit
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/*
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* GM20B GPU GR
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVGPU_GR_GP10B_H_
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#define _NVGPU_GR_GP10B_H_
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struct gpu_ops;
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enum {
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PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
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PASCAL_A = 0xC097,
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PASCAL_COMPUTE_A = 0xC0C0,
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PASCAL_DMA_COPY_A = 0xC0B5,
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};
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
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void gp10b_init_gr(struct gpu_ops *ops);
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struct gr_t18x {
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struct {
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u32 preempt_image_size;
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} ctx_vars;
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};
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struct gr_ctx_desc_t18x {
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struct mem_desc preempt_ctxsw_buffer;
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struct mem_desc spill_ctxsw_buffer;
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struct mem_desc betacb_ctxsw_buffer;
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struct mem_desc pagepool_ctxsw_buffer;
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};
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#define NVGPU_GR_PREEMPTION_MODE_GFXP 1
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#define NVGPU_GR_PREEMPTION_MODE_CILP 3
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#endif
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