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f43897c940
This patch is to enable GR1 before resetting GR0 which is not visible to the driver. Bug 3690950 Change-Id: I8a1907349f5a4354c6b7f95f9904b52738f51f00 Signed-off-by: atanand <atanand@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2758161 (cherry picked from commit 48d925cacf373a97dbdb031a109b83be3bfe2972) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2765635 Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
44 lines
1.7 KiB
C
44 lines
1.7 KiB
C
/*
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* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_GA10B_H
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#define NVGPU_MC_GA10B_H
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#include <nvgpu/types.h>
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#define MC_UNIT_RESET_DELAY_US 20U
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#define MC_ENGINE_RESET_DELAY_US 500U
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struct gk20a;
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int ga10b_mc_poll_device_enable(struct gk20a *g, u32 reg_idx,
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u32 poll_val);
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int ga10b_mc_enable_units(struct gk20a *g, u32 units, bool enable);
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int ga10b_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
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bool enable);
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int ga10b_mc_enable_devtype(struct gk20a *g, u32 devtype, bool enable);
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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void ga10b_mc_elpg_enable(struct gk20a *g);
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#endif
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#endif /* NVGPU_MC_GA10B_H */
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