Tejal Kudav 9865db4e46 gpu: nvgpu: Enumerate priv ring before intr enable ...

Mon subelement needs to access GPC TPC configuration registers
to figure out GPC/TPC count post floor sweeping. These registers
are needed as part of intr handling.
Move priv ring init ahead in RM boot to make sure priv ring
enumeration is done before any unit enables it's interrupts.
This ensures that priv ring is enumerated before any interrupt
handler is run to access GPC/TPC count.

JIRA NVGPU-6528

Change-Id: I8aa6ac182e6dd60a79fa76af6813ea70102316f4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2809442
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

2022-11-23 08:06:17 -08:00

..

nvgpu

gpu: nvgpu: Enumerate priv ring before intr enable

2022-11-23 08:06:17 -08:00

Makefile

nvgpu: remove support of nvgpu driver

2022-06-07 12:24:44 -07:00