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6ed3cffb73
ACR/SEC2 methods to support ACR boot SEC2 falcon JIRA DNVGPU-34 Change-Id: I917be1d6c61a1c1ae61a918f50228ea00492cd50 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161122 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
30 lines
1.1 KiB
C
30 lines
1.1 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SEC2_H_
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#define __SEC2_H_
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int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
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int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
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void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
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u32 dst, u8 *src, u32 size, u8 port);
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void sec2_dump_falcon_stats(struct pmu_gk20a *pmu);
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int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
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void *desc, u32 bl_sz);
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void sec_enable_irq(struct pmu_gk20a *pmu, bool enable);
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void init_pmu_setup_hw1(struct gk20a *g);
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int init_sec2_setup_hw1(struct gk20a *g,
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void *desc, u32 bl_sz);
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#endif /*__SEC2_H_*/
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