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3b9630a366
Use fuse hals instead of direct fuse register reads to make code compatible with multiple chip families. JIRA NVGPU-4663 JIRA NVGPU-4835 JIRA NVGPU-4856 Change-Id: I15889aee38baf6393d11becb7ed995e9f0fd5897 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279629 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
110 lines
3.5 KiB
C
110 lines
3.5 KiB
C
/*
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* GP10B FUSE
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*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/fuse.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "fuse_gm20b.h"
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#include "fuse_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
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int gp10b_fuse_check_priv_security(struct gk20a *g)
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{
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u32 gcplex_config;
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bool is_wpr_enabled = false;
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bool is_auto_fetch_disable = false;
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#ifdef CONFIG_NVGPU_SIM
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
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nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
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nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel");
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return 0;
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}
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#endif
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if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) {
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nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
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return -EINVAL;
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}
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if (g->ops.fuse.fuse_opt_priv_sec_en(g) != 0U) {
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/*
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* all falcons have to boot in LS mode and this needs
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* wpr_enabled set to 1 and vpr_auto_fetch_disable
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* set to 0. In this case gmmu tries to pull wpr
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* and vpr settings from tegra mc
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*/
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nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
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nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
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is_wpr_enabled =
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(gcplex_config & GCPLEX_CONFIG_WPR_ENABLED_MASK) != 0U;
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is_auto_fetch_disable =
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(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
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if (is_wpr_enabled && !is_auto_fetch_disable) {
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if (g->ops.fuse.fuse_opt_sec_debug_en(g) != 0U) {
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nvgpu_log(g, gpu_dbg_info,
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"gcplex_config = 0x%08x, "
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"secure mode: ACR debug",
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gcplex_config);
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} else {
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nvgpu_log(g, gpu_dbg_info,
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"gcplex_config = 0x%08x, "
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"secure mode: ACR non debug",
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gcplex_config);
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}
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} else {
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nvgpu_err(g, "gcplex_config = 0x%08x "
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"invalid wpr_enabled/vpr_auto_fetch_disable "
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"with priv_sec_en", gcplex_config);
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/* do not try to boot GPU */
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return -EINVAL;
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}
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} else {
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nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
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nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
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nvgpu_log(g, gpu_dbg_info,
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"gcplex_config = 0x%08x, non secure mode",
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gcplex_config);
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}
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return 0;
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}
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bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g)
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{
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return nvgpu_readl(g, fuse_opt_ecc_en_r()) != 0U;
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}
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bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g)
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{
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return nvgpu_readl(g,
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fuse_opt_feature_fuses_override_disable_r()) != 0U;
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}
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