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gpu: nvgpu: fuse: use hals instead of direct register reads

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Use fuse hals instead of direct fuse register reads to make
code compatible with multiple chip families.

JIRA NVGPU-4663
JIRA NVGPU-4835
JIRA NVGPU-4856

Change-Id: I15889aee38baf6393d11becb7ed995e9f0fd5897
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279629
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2020-01-15 15:16:20 -08:00
committed by Alex Waterman
parent 993d138f60
commit 3b9630a366
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/fuse/fuse_gp10b_fusa.c
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@@ -53,7 +53,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
return -EINVAL;
}
if (nvgpu_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
if (g->ops.fuse.fuse_opt_priv_sec_en(g) != 0U) {
/*
* all falcons have to boot in LS mode and this needs
* wpr_enabled set to 1 and vpr_auto_fetch_disable
@@ -67,7 +67,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
is_auto_fetch_disable =
(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
if (is_wpr_enabled && !is_auto_fetch_disable) {
if (nvgpu_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
if (g->ops.fuse.fuse_opt_sec_debug_en(g) != 0U) {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR debug",