mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
a70df981e6
ga10b supports floor-sweeping of GPCs. Check for tegra soc fuse info, before making gpcclk requests to BPMP for available GPCs. Bug 3362403 Change-Id: I3f5e2d85b785098ce3a8c8d7d8a5621446e94c15 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2616898 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/fuse.h>
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#include <nvgpu/linux/soc_fuse.h>
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#include <soc/tegra/fuse.h>
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int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
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{
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*id = tegra_sku_info.gpu_speedo_id;
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return 0;
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}
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int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
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}
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int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
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}
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int nvgpu_tegra_fuse_read_opt_gpc_disable(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_OPT_GPC_DISABLE_0, val);
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}
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int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
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{
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u32 lo = 0U;
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u32 hi = 0U;
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int err;
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err = tegra_fuse_readl(FUSE_PDI0, &lo);
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if (err)
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return err;
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err = tegra_fuse_readl(FUSE_PDI1, &hi);
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if (err)
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return err;
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*pdi = ((u64)lo) | (((u64)hi) << 32);
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return 0;
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}
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#ifdef CONFIG_NVGPU_TEGRA_FUSE
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/*
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* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
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* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
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*/
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void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
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{
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tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
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}
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void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
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{
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tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
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}
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#endif /* CONFIG_NVGPU_TEGRA_FUSE */
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