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New tpc_exception_sm_disable hal to disable and tpc_exception_sm_enable hal to enable the sm bit in tpc_exception register. These hals are added to avoid the register access in common gr code. JIRA NVGPU-3016 Change-Id: I21634e2cd3b2b8007081e6f7608ec2da9c74813f Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2088311 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>