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gpu: nvgpu: tu104: fix MISRA Rule 10.4 Violations

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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: I3b725e60f1908a4b3a308736d02600f86929cdd3
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1958306
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sai Nikhil
2018-11-26 13:01:09 +05:30
committed by mobile promotions
parent 4e4e76fd33
commit 1c3e533d98
5 changed files with 33 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/tu104/bios_tu104.c
View File

@@ -29,13 +29,13 @@
#include "nvgpu/hw/tu104/hw_gc6_tu104.h"
#define NV_DEVINIT_VERIFY_TIMEOUT_MS 1000
#define NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US 10
#define NV_DEVINIT_VERIFY_TIMEOUT_MS 1000U
#define NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US 10U
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_MASK \
0xFF
0xFFU
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED \
0xFF
0xFFU
int tu104_bios_verify_devinit(struct gk20a *g)
{

2
drivers/gpu/nvgpu/tu104/fbpa_tu104.c
View File

@@ -48,7 +48,7 @@ static void tu104_fbpa_handle_ecc_intr(struct gk20a *g,
{
u32 status, sec_cnt, ded_cnt;
u32 offset = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) * fbpa_id;
u32 cnt_idx = fbpa_id * 2 + subp_id;
u32 cnt_idx = fbpa_id * 2U + subp_id;
status = gk20a_readl(g, offset + fbpa_0_ecc_status_r(subp_id));

14
drivers/gpu/nvgpu/tu104/fifo_tu104.c
View File

@@ -127,7 +127,7 @@ void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
fifo_runlist_base_lo_ptr_align_shift_v();
runlist_iova_hi = u64_hi32(runlist_iova);
if (count != 0) {
if (count != 0U) {
nvgpu_writel(g, fifo_runlist_base_lo_r(runlist_id),
fifo_runlist_base_lo_ptr_lo_f(runlist_iova_lo) |
nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
@@ -158,12 +158,12 @@ int tu104_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
ret = -ETIMEDOUT;
do {
if ((nvgpu_readl(g, fifo_runlist_submit_info_r(runlist_id)) &
fifo_runlist_submit_info_pending_true_f()) == 0) {
fifo_runlist_submit_info_pending_true_f()) == 0U) {
ret = 0;
break;
}
nvgpu_usleep_range(delay, delay * 2);
nvgpu_usleep_range(delay, delay * 2UL);
delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
} while (nvgpu_timeout_expired(&timeout) == 0);
@@ -251,7 +251,7 @@ int tu104_init_pdb_cache_war(struct gk20a *g)
pdb_addr_hi = u64_hi32(pdb_addr);
nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
ram_in_page_dir_base_lo_w() + (i * PAGE_SIZE / 4),
ram_in_page_dir_base_lo_w() + (i * PAGE_SIZE / 4U),
nvgpu_aperture_mask(g, &g->pdb_cache_war_mem,
ram_in_page_dir_base_target_sys_mem_ncoh_f(),
ram_in_page_dir_base_target_sys_mem_coh_f(),
@@ -262,7 +262,7 @@ int tu104_init_pdb_cache_war(struct gk20a *g)
ram_in_use_ver2_pt_format_true_f());
nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
ram_in_page_dir_base_hi_w() + (i * PAGE_SIZE / 4),
ram_in_page_dir_base_hi_w() + (i * PAGE_SIZE / 4U),
ram_in_page_dir_base_hi_f(pdb_addr_hi));
pdb_addr += PAGE_SIZE;
@@ -273,7 +273,7 @@ int tu104_init_pdb_cache_war(struct gk20a *g)
pdb_addr_hi = u64_hi32(last_bind_pdb_addr);
nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
ram_in_page_dir_base_lo_w() + (256U * PAGE_SIZE / 4),
ram_in_page_dir_base_lo_w() + (256U * PAGE_SIZE / 4U),
nvgpu_aperture_mask(g, &g->pdb_cache_war_mem,
ram_in_page_dir_base_target_sys_mem_ncoh_f(),
ram_in_page_dir_base_target_sys_mem_coh_f(),
@@ -284,7 +284,7 @@ int tu104_init_pdb_cache_war(struct gk20a *g)
ram_in_use_ver2_pt_format_true_f());
nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
ram_in_page_dir_base_hi_w() + (256U * PAGE_SIZE / 4),
ram_in_page_dir_base_hi_w() + (256U * PAGE_SIZE / 4U),
ram_in_page_dir_base_hi_f(pdb_addr_hi));
return 0;

8
drivers/gpu/nvgpu/tu104/gr_tu104.c
View File

@@ -87,8 +87,8 @@ int gr_tu104_init_sw_bundle64(struct gk20a *g)
struct netlist_av64_list *sw_bundle64_init =
&g->netlist_vars->sw_bundle64_init;
for (i = 0; i < sw_bundle64_init->count; i++) {
if (i == 0 ||
for (i = 0U; i < sw_bundle64_init->count; i++) {
if (i == 0U ||
(last_bundle_data_lo != sw_bundle64_init->l[i].value_lo) ||
(last_bundle_data_hi != sw_bundle64_init->l[i].value_hi)) {
nvgpu_writel(g, gr_pipe_bundle_data_r(),
@@ -338,7 +338,7 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
*
* Note 1 PES_PER_GPC case
*/
if (num_pes_per_gpc > 1) {
if (num_pes_per_gpc > 1U) {
offset_in_segment =
(((g->netlist_vars->ctxsw_regs.tpc.count *
num_tpcs) << 2) +
@@ -350,7 +350,7 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
}
} else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
(addr_type == CTXSW_ADDR_TYPE_ETPC)) {
if (num_pes_per_gpc > 1) {
if (num_pes_per_gpc > 1U) {
offset_in_segment =
((g->netlist_vars->ctxsw_regs.tpc.count *
num_tpcs) << 2) +

34
drivers/gpu/nvgpu/tu104/gr_tu104.h
View File

@@ -35,25 +35,25 @@ enum {
TURING_DMA_COPY_A = 0xC5B5,
};
#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528
#define NVC5C0_SET_SKEDCHECK 0x23c
#define NVC5C0_SET_SHADER_CUT_COLLECTOR 0x254
#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528U
#define NVC5C0_SET_SKEDCHECK 0x23cU
#define NVC5C0_SET_SHADER_CUT_COLLECTOR 0x254U
#define NVC5C0_SET_SM_DISP_CTRL 0x250
#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK 0x1
#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0
#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 1
#define NVC5C0_SET_SM_DISP_CTRL 0x250U
#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK 0x1U
#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0U
#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 1U
#define NVC597_SET_SHADER_EXCEPTIONS 0x1528
#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280
#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c
#define NVC597_SET_TEX_IN_DBG 0x10bc
#define NVC597_SET_SKEDCHECK 0x10c0
#define NVC597_SET_BES_CROP_DEBUG3 0x10c4
#define NVC597_SET_BES_CROP_DEBUG4 0x10b0
#define NVC597_SET_SM_DISP_CTRL 0x10c8
#define NVC597_SET_SHADER_CUT_COLLECTOR 0x10d0
#define NVC597_SET_SHADER_EXCEPTIONS 0x1528U
#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280U
#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU
#define NVC597_SET_GO_IDLE_TIMEOUT 0x022cU
#define NVC597_SET_TEX_IN_DBG 0x10bcU
#define NVC597_SET_SKEDCHECK 0x10c0U
#define NVC597_SET_BES_CROP_DEBUG3 0x10c4U
#define NVC597_SET_BES_CROP_DEBUG4 0x10b0U
#define NVC597_SET_SM_DISP_CTRL 0x10c8U
#define NVC597_SET_SHADER_CUT_COLLECTOR 0x10d0U
/* TODO: merge these into global context buffer list in gr_gk20a.h */
#define RTV_CIRCULAR_BUFFER 8