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gpu: nvgpu: fix MISRA 5.6 violation

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Fix following MISRA 5.6 violation.

kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c:50:
  Type: Coding standard violation (MISRA C-2012 Rule 5.6)
kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c:50:
  1. identifier_reuse: Identifier "get_ucode_details" is
     already used to represent a typedef.
kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c:50:
  2. typedef_declaration: Declaring a typedef with identifier
     "get_ucode_details" in remote file "acr_gp106.c".

JIRA NVGPU-1459

Change-Id: Ic5848f251d3be955f20cabcb26a17021b08ae37f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964439
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2018-12-03 21:01:01 +05:30
committed by mobile promotions
parent ac3cb4cc53
commit 4e4e76fd33
2 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
View File

@@ -47,7 +47,8 @@
#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata);
typedef int (*gm20b_get_ucode_details)(struct gk20a *g,
struct flcn_ucode_img *udata);
/*Externs*/
@@ -69,7 +70,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm);
/*Globals*/
static get_ucode_details pmu_acr_supp_ucode_list[] = {
static gm20b_get_ucode_details pmu_acr_supp_ucode_list[] = {
pmu_ucode_details,
fecs_ucode_details,
gpccs_ucode_details,

6
drivers/gpu/nvgpu/common/pmu/acr_gp106.c
View File

@@ -50,8 +50,8 @@
#define gp106_dbg_pmu(g, fmt, arg...) \
nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
typedef int (*get_ucode_details)(struct gk20a *g,
struct flcn_ucode_img_v1 *udata);
typedef int (*gp106_get_ucode_details)(struct gk20a *g,
struct flcn_ucode_img_v1 *udata);
/* Both size and address of WPR need to be 128K-aligned */
#define WPR_ALIGNMENT 0x20000
@@ -64,7 +64,7 @@ typedef int (*get_ucode_details)(struct gk20a *g,
/*Forwards*/
/*Globals*/
static get_ucode_details pmu_acr_supp_ucode_list[] = {
static gp106_get_ucode_details pmu_acr_supp_ucode_list[] = {
pmu_ucode_details,
fecs_ucode_details,
gpccs_ucode_details,