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e8486f0b25
Some of the engine queue related defines are shared by PMU, SEC2 and queue implementations and currently in gpmuif_cmn.h. Let us add engine_queue.h header file to club all those defines together. JIRA NVGPU-1994 Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2019414 GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
72 lines
2.6 KiB
C
72 lines
2.6 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ENGINE_MEM_QUEUE_H
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#define NVGPU_ENGINE_MEM_QUEUE_H
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#include <nvgpu/types.h>
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struct nvgpu_falcon;
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struct nvgpu_engine_mem_queue;
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struct nvgpu_engine_mem_queue_params {
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struct gk20a *g;
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u32 flcn_id;
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/* Queue Type (queue_type) */
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u8 queue_type;
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/* current write position */
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u32 position;
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/* physical dmem offset where this queue begins */
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u32 offset;
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/* logical queue identifier */
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u32 id;
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/* physical queue index */
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u32 index;
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/* in bytes */
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u32 size;
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/* open-flag */
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u32 oflag;
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/* engine specific ops */
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int (*queue_head)(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *head, bool set);
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int (*queue_tail)(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *tail, bool set);
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};
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/* queue public functions */
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int nvgpu_engine_mem_queue_init(struct nvgpu_engine_mem_queue **queue_p,
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struct nvgpu_engine_mem_queue_params params);
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bool nvgpu_engine_mem_queue_is_empty(struct nvgpu_engine_mem_queue *queue);
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int nvgpu_engine_mem_queue_rewind(struct nvgpu_falcon *flcn,
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struct nvgpu_engine_mem_queue *queue);
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int nvgpu_engine_mem_queue_pop(struct nvgpu_falcon *flcn,
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struct nvgpu_engine_mem_queue *queue, void *data, u32 size,
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u32 *bytes_read);
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int nvgpu_engine_mem_queue_push(struct nvgpu_falcon *flcn,
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struct nvgpu_engine_mem_queue *queue, void *data, u32 size);
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void nvgpu_engine_mem_queue_free(struct nvgpu_engine_mem_queue **queue_p);
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u32 nvgpu_engine_mem_queue_get_size(struct nvgpu_engine_mem_queue *queue);
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#endif /* NVGPU_ENGINE_MEM_QUEUE_H */
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