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75e4e7c9bc
This fixes a number of miscellaneous MISRA 10.3 violations in common/pmu/clk/ for assignment of objects of different size or essential type. JIRA NVGPU-1008 Change-Id: If93aa9fc4f0f49ea678e39111f323ef4d53f5ec5 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008771 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_FLL_H
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#define NVGPU_CLK_FLL_H
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/boardobjgrpmask.h>
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struct fll_device;
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struct avfsfllobjs;
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typedef int fll_lut_broadcast_slave_register(struct gk20a *g,
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struct avfsfllobjs *pfllobjs,
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struct fll_device *pfll,
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struct fll_device *pfll_slave);
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struct fll_device {
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struct boardobj super;
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u8 id;
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u8 mdiv;
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u16 input_freq_mhz;
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u32 clk_domain;
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u8 vin_idx_logic;
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u8 vin_idx_sram;
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u8 rail_idx_for_lut;
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struct nv_pmu_clk_lut_device_desc lut_device;
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struct nv_pmu_clk_regime_desc regime_desc;
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u8 min_freq_vfe_idx;
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u8 freq_ctrl_idx;
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u8 target_regime_id_override;
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bool b_skip_pldiv_below_dvco_min;
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bool b_dvco_1x;
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struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask;
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fll_lut_broadcast_slave_register *lut_broadcast_slave_register;
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};
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#define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \
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((pclk)->avfs_fllobjs.lut_num_entries)
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#define CLK_FLL_LUT_MIN_VOLTAGE_UV(pclk) \
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((pclk)->avfs_fllobjs.lut_min_voltage_uv)
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#define CLK_FLL_LUT_STEP_SIZE_UV(pclk) \
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((pclk)->avfs_fllobjs.lut_step_size_uv)
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#endif /* NVGPU_CLK_FLL_H */
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