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5cde4c2140
Extract out the HAL ops' implementation that now belongs to the channel unit. This unit is responsible for channel register accesses and the like (ccsr_*). Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the rest of the naming. Same with channel_gv11b_unbind. Jira NVGPU-1307 Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
113 lines
4.8 KiB
C
113 lines
4.8 KiB
C
/*
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* GV11B Fifo
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*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_GV11B_H
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#define FIFO_GV11B_H
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#define PBDMA_SUBDEVICE_ID 1U
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#define FIFO_INVAL_PBDMA_ID (~U32(0U))
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#define FIFO_INVAL_VEID (~U32(0U))
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/* engine context-switch request occurred while the engine was in reset */
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#define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005U
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/*
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* ERROR_CODE_BAD_TSG indicates that Host encountered a badly formed TSG header
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* or a badly formed channel type runlist entry in the runlist. This is typically
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* caused by encountering a new TSG entry in the middle of a TSG definition.
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* A channel type entry having wrong runqueue selector can also cause this.
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* Additionally this error code can indicate when a channel is encountered on
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* the runlist which is outside of a TSG.
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*/
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#define SCHED_ERROR_CODE_BAD_TSG 0x00000020U
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/* can be removed after runque support is added */
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#define GR_RUNQUE 0U /* pbdma 0 */
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#define ASYNC_CE_RUNQUE 2U /* pbdma 2 */
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#define CHANNEL_INFO_VEID0 0U
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#define MAX_PRE_SI_RETRIES 200000U /* 1G/500KHz * 100 */
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struct gpu_ops;
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void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
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struct tsg_gk20a *tsg,
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u32 faulted_pbdma, u32 faulted_engine);
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void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
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u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id);
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int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
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u64 gpfifo_base, u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags);
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u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c);
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u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c);
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void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c);
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bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid);
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void gv11b_dump_channel_status_ramfc(struct gk20a *g,
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struct gk20a_debug_output *o,
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struct nvgpu_channel_dump_info *info);
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void gv11b_capture_channel_ram_dump(struct gk20a *g,
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struct channel_gk20a *ch,
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struct nvgpu_channel_dump_info *info);
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void gv11b_dump_eng_status(struct gk20a *g,
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struct gk20a_debug_output *o);
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u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g);
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int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
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unsigned int id_type);
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int gv11b_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
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int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
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int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg);
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void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
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u32 id, unsigned int id_type, unsigned int rc_type,
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struct mmu_fault_info *mmfault);
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void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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int gv11b_init_fifo_reset_enable_hw(struct gk20a *g);
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bool gv11b_fifo_handle_sched_error(struct gk20a *g);
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bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr);
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unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g,
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u32 pbdma_id, u32 pbdma_intr_0,
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u32 *handled, u32 *error_notifier);
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unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g,
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u32 pbdma_id, u32 pbdma_intr_1,
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u32 *handled, u32 *error_notifier);
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void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
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struct tsg_gk20a *tsg);
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void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
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struct tsg_gk20a *tsg);
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int gv11b_init_fifo_setup_hw(struct gk20a *g);
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void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch);
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u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g);
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void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
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struct channel_gk20a *ch, struct nvgpu_mem *mem);
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void gv11b_userd_writeback_config(struct gk20a *g);
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void gv11b_ring_channel_doorbell(struct channel_gk20a *c);
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u64 gv11b_fifo_usermode_base(struct gk20a *g);
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u32 gv11b_fifo_doorbell_token(struct channel_gk20a *c);
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#endif
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