mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
7189630e7c
Now that the moved HAL ops from fifo are in channel, rename the implementations to match. Jira NVGPU-1307 Change-Id: I7b9336f506c9e71bcd0af98886216958bd6695eb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017264 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
721 lines
25 KiB
C
721 lines
25 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "common/bus/bus_gk20a.h"
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#include "common/bus/bus_gm20b.h"
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#include "common/priv_ring/priv_ring_gm20b.h"
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#include "common/priv_ring/priv_ring_gp10b.h"
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#include "common/clock_gating/gp10b_gating_reglist.h"
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#include "common/fb/fb_gm20b.h"
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#include "common/fb/fb_gp10b.h"
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#include "common/netlist/netlist_gp10b.h"
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#include "common/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
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#include "common/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
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#include "common/gr/config/gr_config_gm20b.h"
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#include "common/therm/therm_gm20b.h"
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#include "common/therm/therm_gp10b.h"
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#include "common/ltc/ltc_gm20b.h"
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#include "common/ltc/ltc_gp10b.h"
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#include "common/fuse/fuse_gm20b.h"
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#include "common/fuse/fuse_gp10b.h"
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#include "common/regops/regops_gp10b.h"
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#include "common/fifo/runlist_gk20a.h"
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#include "common/fifo/channel_gm20b.h"
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#include "vgpu/fifo_vgpu.h"
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#include "vgpu/gr_vgpu.h"
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#include "vgpu/ltc_vgpu.h"
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#include "vgpu/mm_vgpu.h"
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#include "vgpu/dbg_vgpu.h"
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#include "vgpu/fecs_trace_vgpu.h"
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#include "vgpu/css_vgpu.h"
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#include "gp10b/gp10b.h"
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#include "gp10b/hal_gp10b.h"
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#include "vgpu/gm20b/vgpu_gr_gm20b.h"
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#include "vgpu_gr_gp10b.h"
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#include "vgpu_mm_gp10b.h"
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#include "vgpu_fuse_gp10b.h"
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#include "common/falcon/falcon_gk20a.h"
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#include "common/sync/syncpt_cmdbuf_gk20a.h"
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#include "common/sync/sema_cmdbuf_gk20a.h"
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#include "gp10b/mm_gp10b.h"
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#include "gp10b/ce_gp10b.h"
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#include "gp10b/gr_gp10b.h"
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#include "gp10b/fifo_gp10b.h"
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#include "gp10b/clk_arb_gp10b.h"
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#include "gm20b/gr_gm20b.h"
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#include "gm20b/fifo_gm20b.h"
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#include "gm20b/mm_gm20b.h"
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#include "gk20a/fecs_trace_gk20a.h"
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#include <nvgpu/debugger.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/error_notifier.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
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static const struct gpu_ops vgpu_gp10b_ops = {
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.ltc = {
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.determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
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.set_zbc_color_entry = NULL,
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.set_zbc_depth_entry = NULL,
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.init_cbc = NULL,
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.init_fs_state = vgpu_ltc_init_fs_state,
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.init_comptags = vgpu_ltc_init_comptags,
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.cbc_ctrl = NULL,
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.isr = NULL,
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.cbc_fix_config = NULL,
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.flush = NULL,
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.set_enabled = NULL,
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.pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
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.is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
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.is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
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.split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
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.split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
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},
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.ce2 = {
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.isr_stall = NULL,
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.isr_nonstall = NULL,
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.get_num_pce = vgpu_ce_get_num_pce,
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},
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.gr = {
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.get_patch_slots = gr_gk20a_get_patch_slots,
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.init_gpc_mmu = NULL,
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.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
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.cb_size_default = gr_gp10b_cb_size_default,
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.calc_global_ctx_buffer_size =
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gr_gp10b_calc_global_ctx_buffer_size,
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.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
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.commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
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.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
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.commit_global_pagepool = gr_gp10b_commit_global_pagepool,
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.handle_sw_method = NULL,
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.set_alpha_circular_buffer_size = NULL,
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.set_circular_buffer_size = NULL,
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.enable_hww_exceptions = NULL,
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.is_valid_class = gr_gp10b_is_valid_class,
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.is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
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.is_valid_compute_class = gr_gp10b_is_valid_compute_class,
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.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
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.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
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.init_fs_state = vgpu_gr_init_fs_state,
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.set_hww_esr_report_mask = NULL,
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.falcon_load_ucode = NULL,
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.load_ctxsw_ucode = NULL,
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.set_gpc_tpc_mask = NULL,
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.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
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.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
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.get_zcull_info = vgpu_gr_get_zcull_info,
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.is_tpc_addr = gr_gm20b_is_tpc_addr,
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.get_tpc_num = gr_gm20b_get_tpc_num,
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.detect_sm_arch = vgpu_gr_detect_sm_arch,
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.add_zbc_color = NULL,
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.add_zbc_depth = NULL,
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.zbc_set_table = vgpu_gr_add_zbc,
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.zbc_query_table = vgpu_gr_query_zbc,
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.pmu_save_zbc = NULL,
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.add_zbc = NULL,
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.pagepool_default_size = gr_gp10b_pagepool_default_size,
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.init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
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.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
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.free_gr_ctx = vgpu_gr_free_gr_ctx,
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.init_ctxsw_preemption_mode =
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vgpu_gr_gp10b_init_ctxsw_preemption_mode,
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.update_ctxsw_preemption_mode =
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gr_gp10b_update_ctxsw_preemption_mode,
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.dump_gr_regs = NULL,
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.update_pc_sampling = vgpu_gr_update_pc_sampling,
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.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
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.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
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.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
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.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
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.get_max_fbps_count = vgpu_gr_get_max_fbps_count,
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.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
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.wait_empty = NULL,
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.init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
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.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
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.bpt_reg_info = NULL,
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.get_access_map = gr_gp10b_get_access_map,
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.handle_fecs_error = NULL,
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.handle_sm_exception = NULL,
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.handle_tex_exception = NULL,
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.enable_gpc_exceptions = NULL,
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.enable_exceptions = NULL,
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.get_lrf_tex_ltc_dram_override = NULL,
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.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
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.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
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.record_sm_error_state = gm20b_gr_record_sm_error_state,
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.clear_sm_error_state = vgpu_gr_clear_sm_error_state,
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.suspend_contexts = vgpu_gr_suspend_contexts,
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.resume_contexts = vgpu_gr_resume_contexts,
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.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
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.init_sm_id_table = vgpu_gr_init_sm_id_table,
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.load_smid_config = NULL,
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.program_sm_id_numbering = NULL,
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.setup_rop_mapping = NULL,
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.program_zcull_mapping = NULL,
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.commit_global_timeslice = NULL,
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.commit_inst = vgpu_gr_commit_inst,
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.load_tpc_mask = NULL,
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.trigger_suspend = NULL,
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.wait_for_pause = gr_gk20a_wait_for_pause,
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.resume_from_pause = NULL,
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.clear_sm_errors = gr_gk20a_clear_sm_errors,
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.tpc_enabled_exceptions = NULL,
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.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
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.sm_debugger_attached = NULL,
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.suspend_single_sm = NULL,
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.suspend_all_sms = NULL,
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.resume_single_sm = NULL,
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.resume_all_sms = NULL,
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.get_sm_hww_warp_esr = NULL,
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.get_sm_hww_global_esr = NULL,
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.get_sm_no_lock_down_hww_global_esr_mask =
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gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
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.lock_down_sm = NULL,
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.wait_for_sm_lock_down = NULL,
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.clear_sm_hww = NULL,
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.init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
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.get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
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.disable_rd_coalesce = NULL,
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.set_boosted_ctx = NULL,
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.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
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.set_czf_bypass = NULL,
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.init_czf_bypass = gr_gp10b_init_czf_bypass,
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.pre_process_sm_exception = NULL,
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.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
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.init_preemption_state = NULL,
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.set_bes_crop_debug3 = NULL,
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.set_bes_crop_debug4 = NULL,
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.set_ctxsw_preemption_mode =
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vgpu_gr_gp10b_set_ctxsw_preemption_mode,
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.init_gfxp_wfi_timeout_count =
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gr_gp10b_init_gfxp_wfi_timeout_count,
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.get_max_gfxp_wfi_timeout_count =
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gr_gp10b_get_max_gfxp_wfi_timeout_count,
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.add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
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.add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
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.decode_priv_addr = gr_gk20a_decode_priv_addr,
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.create_priv_addr_table = gr_gk20a_create_priv_addr_table,
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.get_pmm_per_chiplet_offset =
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gr_gm20b_get_pmm_per_chiplet_offset,
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.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
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.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
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.commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
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.get_offset_in_gpccs_segment =
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gr_gk20a_get_offset_in_gpccs_segment,
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.set_debug_mode = gm20b_gr_set_debug_mode,
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.ctxsw_prog = {
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.hw_get_fecs_header_size =
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gm20b_ctxsw_prog_hw_get_fecs_header_size,
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.hw_get_gpccs_header_size =
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gm20b_ctxsw_prog_hw_get_gpccs_header_size,
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.hw_get_extended_buffer_segments_size_in_bytes =
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gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes,
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.hw_extended_marker_size_in_bytes =
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gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes,
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.hw_get_perf_counter_control_register_stride =
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gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride,
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.get_main_image_ctx_id =
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gm20b_ctxsw_prog_get_main_image_ctx_id,
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.get_patch_count = gm20b_ctxsw_prog_get_patch_count,
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.set_patch_count = gm20b_ctxsw_prog_set_patch_count,
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.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
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.set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr,
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.set_zcull = gm20b_ctxsw_prog_set_zcull,
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.set_zcull_mode_no_ctxsw =
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gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw,
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.is_zcull_mode_separate_buffer =
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gm20b_ctxsw_prog_is_zcull_mode_separate_buffer,
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.set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr,
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.set_pm_mode = gm20b_ctxsw_prog_set_pm_mode,
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.set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode,
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.hw_get_pm_mode_no_ctxsw =
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gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw,
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.hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw,
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.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
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.set_compute_preemption_mode_cta =
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gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
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.set_compute_preemption_mode_cilp =
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gp10b_ctxsw_prog_set_compute_preemption_mode_cilp,
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.set_graphics_preemption_mode_gfxp =
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gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp,
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.set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled,
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.set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling,
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.set_priv_access_map_config_mode =
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gm20b_ctxsw_prog_set_priv_access_map_config_mode,
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.set_priv_access_map_addr =
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gm20b_ctxsw_prog_set_priv_access_map_addr,
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.disable_verif_features =
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gm20b_ctxsw_prog_disable_verif_features,
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.check_main_image_header_magic =
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gm20b_ctxsw_prog_check_main_image_header_magic,
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.check_local_header_magic =
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gm20b_ctxsw_prog_check_local_header_magic,
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.get_num_gpcs = gm20b_ctxsw_prog_get_num_gpcs,
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.get_num_tpcs = gm20b_ctxsw_prog_get_num_tpcs,
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.get_extended_buffer_size_offset =
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gm20b_ctxsw_prog_get_extended_buffer_size_offset,
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.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
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.get_local_priv_register_ctl_offset =
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gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
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.hw_get_ts_tag_invalid_timestamp =
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gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
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.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
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.hw_record_ts_timestamp =
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gm20b_ctxsw_prog_hw_record_ts_timestamp,
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.hw_get_ts_record_size_in_bytes =
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gm20b_ctxsw_prog_hw_get_ts_record_size_in_bytes,
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.is_ts_valid_record = gm20b_ctxsw_prog_is_ts_valid_record,
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.get_ts_buffer_aperture_mask =
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gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
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.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
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.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
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.set_pmu_options_boost_clock_frequencies = NULL,
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.set_full_preemption_ptr =
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gp10b_ctxsw_prog_set_full_preemption_ptr,
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.dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats,
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},
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.config = {
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.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
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}
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},
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.fb = {
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.init_hw = NULL,
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.init_fs_state = NULL,
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.set_mmu_page_size = NULL,
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.set_use_full_comp_tag_line = NULL,
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.compression_page_size = gp10b_fb_compression_page_size,
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.compressible_page_size = gp10b_fb_compressible_page_size,
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.compression_align_mask = gm20b_fb_compression_align_mask,
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.vpr_info_fetch = NULL,
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.dump_vpr_info = NULL,
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.dump_wpr_info = NULL,
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.read_wpr_info = NULL,
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.is_debug_mode_enabled = NULL,
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.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
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.tlb_invalidate = vgpu_mm_tlb_invalidate,
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},
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.clock_gating = {
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.slcg_bus_load_gating_prod = NULL,
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.slcg_ce2_load_gating_prod = NULL,
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.slcg_chiplet_load_gating_prod = NULL,
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.slcg_ctxsw_firmware_load_gating_prod = NULL,
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.slcg_fb_load_gating_prod = NULL,
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.slcg_fifo_load_gating_prod = NULL,
|
|
.slcg_gr_load_gating_prod = NULL,
|
|
.slcg_ltc_load_gating_prod = NULL,
|
|
.slcg_perf_load_gating_prod = NULL,
|
|
.slcg_priring_load_gating_prod = NULL,
|
|
.slcg_pmu_load_gating_prod = NULL,
|
|
.slcg_therm_load_gating_prod = NULL,
|
|
.slcg_xbar_load_gating_prod = NULL,
|
|
.blcg_bus_load_gating_prod = NULL,
|
|
.blcg_ce_load_gating_prod = NULL,
|
|
.blcg_ctxsw_firmware_load_gating_prod = NULL,
|
|
.blcg_fb_load_gating_prod = NULL,
|
|
.blcg_fifo_load_gating_prod = NULL,
|
|
.blcg_gr_load_gating_prod = NULL,
|
|
.blcg_ltc_load_gating_prod = NULL,
|
|
.blcg_pwr_csb_load_gating_prod = NULL,
|
|
.blcg_pmu_load_gating_prod = NULL,
|
|
.blcg_xbar_load_gating_prod = NULL,
|
|
.pg_gr_load_gating_prod = NULL,
|
|
},
|
|
.fifo = {
|
|
.init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
|
|
.alloc_inst = vgpu_channel_alloc_inst,
|
|
.free_inst = vgpu_channel_free_inst,
|
|
.setup_ramfc = vgpu_channel_setup_ramfc,
|
|
.default_timeslice_us = vgpu_fifo_default_timeslice_us,
|
|
.setup_userd = gk20a_fifo_setup_userd,
|
|
.userd_gp_get = gk20a_fifo_userd_gp_get,
|
|
.userd_gp_put = gk20a_fifo_userd_gp_put,
|
|
.userd_pb_get = gk20a_fifo_userd_pb_get,
|
|
.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
|
|
.preempt_channel = vgpu_fifo_preempt_channel,
|
|
.preempt_tsg = vgpu_fifo_preempt_tsg,
|
|
.enable_tsg = vgpu_enable_tsg,
|
|
.disable_tsg = gk20a_disable_tsg,
|
|
.tsg_verify_channel_status = NULL,
|
|
.tsg_verify_status_ctx_reload = NULL,
|
|
.trigger_mmu_fault = NULL,
|
|
.get_mmu_fault_info = NULL,
|
|
.get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc,
|
|
.get_mmu_fault_client_desc = gp10b_fifo_get_mmu_fault_client_desc,
|
|
.get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc,
|
|
.wait_engine_idle = vgpu_fifo_wait_engine_idle,
|
|
.get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
|
|
.tsg_set_timeslice = vgpu_tsg_set_timeslice,
|
|
.tsg_open = vgpu_tsg_open,
|
|
.tsg_release = vgpu_tsg_release,
|
|
.force_reset_ch = vgpu_fifo_force_reset_ch,
|
|
.init_engine_info = vgpu_fifo_init_engine_info,
|
|
.get_engines_mask_on_id = NULL,
|
|
.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
|
|
.dump_pbdma_status = NULL,
|
|
.dump_eng_status = NULL,
|
|
.dump_channel_status_ramfc = NULL,
|
|
.capture_channel_ram_dump = NULL,
|
|
.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
|
|
.is_preempt_pending = NULL,
|
|
.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
|
|
.reset_enable_hw = NULL,
|
|
.teardown_ch_tsg = NULL,
|
|
.handle_sched_error = NULL,
|
|
.handle_pbdma_intr_0 = NULL,
|
|
.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
|
|
.tsg_bind_channel = vgpu_tsg_bind_channel,
|
|
.tsg_unbind_channel = vgpu_tsg_unbind_channel,
|
|
.post_event_id = gk20a_tsg_event_id_post_event,
|
|
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
|
|
.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
|
|
.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
|
|
.channel_suspend = gk20a_channel_suspend,
|
|
.channel_resume = gk20a_channel_resume,
|
|
.set_error_notifier = nvgpu_set_error_notifier,
|
|
.setup_sw = gk20a_init_fifo_setup_sw,
|
|
.resetup_ramfc = NULL,
|
|
.set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask,
|
|
},
|
|
.sync = {
|
|
#ifdef CONFIG_TEGRA_GK20A_NVHOST
|
|
.alloc_syncpt_buf = gk20a_alloc_syncpt_buf,
|
|
.free_syncpt_buf = gk20a_free_syncpt_buf,
|
|
.add_syncpt_wait_cmd = gk20a_add_syncpt_wait_cmd,
|
|
.get_syncpt_wait_cmd_size = gk20a_get_syncpt_wait_cmd_size,
|
|
.get_syncpt_incr_per_release =
|
|
gk20a_get_syncpt_incr_per_release,
|
|
.add_syncpt_incr_cmd = gk20a_add_syncpt_incr_cmd,
|
|
.get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size,
|
|
.get_sync_ro_map = NULL,
|
|
#endif
|
|
.get_sema_wait_cmd_size = gk20a_get_sema_wait_cmd_size,
|
|
.get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size,
|
|
.add_sema_cmd = gk20a_add_sema_cmd,
|
|
},
|
|
.runlist = {
|
|
.reschedule_runlist = NULL,
|
|
.update_for_channel = vgpu_runlist_update_for_channel,
|
|
.reload = vgpu_runlist_reload,
|
|
.set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
|
|
.eng_runlist_base_size = gk20a_fifo_runlist_base_size,
|
|
.runlist_entry_size = NULL,
|
|
.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
|
|
.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
|
|
.runlist_hw_submit = NULL,
|
|
.runlist_wait_pending = NULL,
|
|
},
|
|
.channel = {
|
|
.bind = vgpu_channel_bind,
|
|
.unbind = vgpu_channel_unbind,
|
|
.enable = vgpu_channel_enable,
|
|
.disable = vgpu_channel_disable,
|
|
.count = gm20b_channel_count,
|
|
},
|
|
.netlist = {
|
|
.get_netlist_name = gp10b_netlist_get_name,
|
|
.is_fw_defined = gp10b_netlist_is_firmware_defined,
|
|
},
|
|
#ifdef CONFIG_GK20A_CTXSW_TRACE
|
|
.fecs_trace = {
|
|
.alloc_user_buffer = vgpu_alloc_user_buffer,
|
|
.free_user_buffer = vgpu_free_user_buffer,
|
|
.mmap_user_buffer = vgpu_mmap_user_buffer,
|
|
.init = vgpu_fecs_trace_init,
|
|
.deinit = vgpu_fecs_trace_deinit,
|
|
.enable = vgpu_fecs_trace_enable,
|
|
.disable = vgpu_fecs_trace_disable,
|
|
.is_enabled = vgpu_fecs_trace_is_enabled,
|
|
.reset = NULL,
|
|
.flush = NULL,
|
|
.poll = vgpu_fecs_trace_poll,
|
|
.bind_channel = NULL,
|
|
.unbind_channel = NULL,
|
|
.max_entries = vgpu_fecs_trace_max_entries,
|
|
.set_filter = vgpu_fecs_trace_set_filter,
|
|
.get_buffer_full_mailbox_val =
|
|
gk20a_fecs_trace_get_buffer_full_mailbox_val,
|
|
},
|
|
#endif /* CONFIG_GK20A_CTXSW_TRACE */
|
|
.mm = {
|
|
.gmmu_map = vgpu_gp10b_locked_gmmu_map,
|
|
.gmmu_unmap = vgpu_locked_gmmu_unmap,
|
|
.vm_bind_channel = vgpu_vm_bind_channel,
|
|
.fb_flush = vgpu_mm_fb_flush,
|
|
.l2_invalidate = vgpu_mm_l2_invalidate,
|
|
.l2_flush = vgpu_mm_l2_flush,
|
|
.cbc_clean = NULL,
|
|
.set_big_page_size = gm20b_mm_set_big_page_size,
|
|
.get_big_page_sizes = gm20b_mm_get_big_page_sizes,
|
|
.get_default_big_page_size = gp10b_mm_get_default_big_page_size,
|
|
.gpu_phys_addr = gm20b_gpu_phys_addr,
|
|
.get_iommu_bit = gk20a_mm_get_iommu_bit,
|
|
.get_mmu_levels = gp10b_mm_get_mmu_levels,
|
|
.init_pdb = gp10b_mm_init_pdb,
|
|
.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
|
|
.is_bar1_supported = gm20b_mm_is_bar1_supported,
|
|
.init_inst_block = gk20a_init_inst_block,
|
|
.mmu_fault_pending = NULL,
|
|
.init_bar2_vm = gp10b_init_bar2_vm,
|
|
.remove_bar2_vm = gp10b_remove_bar2_vm,
|
|
.get_kind_invalid = gm20b_get_kind_invalid,
|
|
.get_kind_pitch = gm20b_get_kind_pitch,
|
|
.bar1_map_userd = vgpu_mm_bar1_map_userd,
|
|
},
|
|
.pramin = {
|
|
.data032_r = NULL,
|
|
},
|
|
.therm = {
|
|
.init_therm_setup_hw = NULL,
|
|
.init_elcg_mode = NULL,
|
|
.init_blcg_mode = NULL,
|
|
.elcg_init_idle_filters = NULL,
|
|
},
|
|
.pmu = {
|
|
.pmu_setup_elpg = NULL,
|
|
.pmu_get_queue_head = NULL,
|
|
.pmu_get_queue_head_size = NULL,
|
|
.pmu_get_queue_tail = NULL,
|
|
.pmu_get_queue_tail_size = NULL,
|
|
.pmu_queue_head = NULL,
|
|
.pmu_queue_tail = NULL,
|
|
.pmu_msgq_tail = NULL,
|
|
.pmu_mutex_size = NULL,
|
|
.pmu_mutex_acquire = NULL,
|
|
.pmu_mutex_release = NULL,
|
|
.pmu_is_interrupted = NULL,
|
|
.pmu_isr = NULL,
|
|
.pmu_init_perfmon_counter = NULL,
|
|
.pmu_pg_idle_counter_config = NULL,
|
|
.pmu_read_idle_counter = NULL,
|
|
.pmu_reset_idle_counter = NULL,
|
|
.pmu_read_idle_intr_status = NULL,
|
|
.pmu_clear_idle_intr_status = NULL,
|
|
.pmu_dump_elpg_stats = NULL,
|
|
.pmu_dump_falcon_stats = NULL,
|
|
.pmu_enable_irq = NULL,
|
|
.write_dmatrfbase = NULL,
|
|
.pmu_elpg_statistics = NULL,
|
|
.pmu_init_perfmon = NULL,
|
|
.pmu_perfmon_start_sampling = NULL,
|
|
.pmu_perfmon_stop_sampling = NULL,
|
|
.pmu_pg_init_param = NULL,
|
|
.pmu_pg_supported_engines_list = NULL,
|
|
.pmu_pg_engines_feature_list = NULL,
|
|
.dump_secure_fuses = NULL,
|
|
.reset_engine = NULL,
|
|
.is_engine_in_reset = NULL,
|
|
},
|
|
.clk_arb = {
|
|
.check_clk_arb_support = gp10b_check_clk_arb_support,
|
|
.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
|
|
.get_arbiter_f_points = gp10b_get_arbiter_f_points,
|
|
.get_arbiter_clk_range = gp10b_get_arbiter_clk_range,
|
|
.get_arbiter_clk_default = gp10b_get_arbiter_clk_default,
|
|
.arbiter_clk_init = gp10b_init_clk_arbiter,
|
|
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
|
|
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
|
|
},
|
|
.regops = {
|
|
.exec_regops = vgpu_exec_regops,
|
|
.get_global_whitelist_ranges =
|
|
gp10b_get_global_whitelist_ranges,
|
|
.get_global_whitelist_ranges_count =
|
|
gp10b_get_global_whitelist_ranges_count,
|
|
.get_context_whitelist_ranges =
|
|
gp10b_get_context_whitelist_ranges,
|
|
.get_context_whitelist_ranges_count =
|
|
gp10b_get_context_whitelist_ranges_count,
|
|
.get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
|
|
.get_runcontrol_whitelist_count =
|
|
gp10b_get_runcontrol_whitelist_count,
|
|
.get_qctl_whitelist = gp10b_get_qctl_whitelist,
|
|
.get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
|
|
},
|
|
.mc = {
|
|
.intr_mask = NULL,
|
|
.intr_enable = NULL,
|
|
.intr_unit_config = NULL,
|
|
.isr_stall = NULL,
|
|
.intr_stall = NULL,
|
|
.intr_stall_pause = NULL,
|
|
.intr_stall_resume = NULL,
|
|
.intr_nonstall = NULL,
|
|
.intr_nonstall_pause = NULL,
|
|
.intr_nonstall_resume = NULL,
|
|
.isr_nonstall = NULL,
|
|
.enable = NULL,
|
|
.disable = NULL,
|
|
.reset = NULL,
|
|
.is_intr1_pending = NULL,
|
|
.log_pending_intrs = NULL,
|
|
.reset_mask = NULL,
|
|
.is_enabled = NULL,
|
|
.fb_reset = NULL,
|
|
},
|
|
.debug = {
|
|
.show_dump = NULL,
|
|
},
|
|
#ifdef NVGPU_DEBUGGER
|
|
.debugger = {
|
|
.post_events = nvgpu_dbg_gpu_post_events,
|
|
.dbg_set_powergate = vgpu_dbg_set_powergate,
|
|
.check_and_set_global_reservation =
|
|
vgpu_check_and_set_global_reservation,
|
|
.check_and_set_context_reservation =
|
|
vgpu_check_and_set_context_reservation,
|
|
.release_profiler_reservation =
|
|
vgpu_release_profiler_reservation,
|
|
},
|
|
#endif
|
|
.perfbuf = {
|
|
.perfbuf_enable = vgpu_perfbuffer_enable,
|
|
.perfbuf_disable = vgpu_perfbuffer_disable,
|
|
},
|
|
.bus = {
|
|
.init_hw = NULL,
|
|
.isr = NULL,
|
|
.bar1_bind = NULL,
|
|
.bar2_bind = NULL,
|
|
.set_bar0_window = NULL,
|
|
},
|
|
.ptimer = {
|
|
.isr = NULL,
|
|
.read_ptimer = vgpu_read_ptimer,
|
|
.get_timestamps_zipper = vgpu_get_timestamps_zipper,
|
|
},
|
|
#if defined(CONFIG_GK20A_CYCLE_STATS)
|
|
.css = {
|
|
.enable_snapshot = vgpu_css_enable_snapshot_buffer,
|
|
.disable_snapshot = vgpu_css_release_snapshot_buffer,
|
|
.check_data_available = vgpu_css_flush_snapshots,
|
|
.detach_snapshot = vgpu_css_detach,
|
|
.set_handled_snapshots = NULL,
|
|
.allocate_perfmon_ids = NULL,
|
|
.release_perfmon_ids = NULL,
|
|
},
|
|
#endif
|
|
.falcon = {
|
|
.falcon_hal_sw_init = NULL,
|
|
.falcon_hal_sw_free = NULL,
|
|
},
|
|
.priv_ring = {
|
|
.enable_priv_ring = NULL,
|
|
.isr = NULL,
|
|
.set_ppriv_timeout_settings = NULL,
|
|
.enum_ltc = NULL,
|
|
},
|
|
.fuse = {
|
|
.check_priv_security = vgpu_gp10b_fuse_check_priv_security,
|
|
.is_opt_ecc_enable = NULL,
|
|
.is_opt_feature_override_disable = NULL,
|
|
.fuse_status_opt_fbio = NULL,
|
|
.fuse_status_opt_fbp = NULL,
|
|
.fuse_status_opt_rop_l2_fbp = NULL,
|
|
.fuse_status_opt_tpc_gpc = NULL,
|
|
.fuse_ctrl_opt_tpc_gpc = NULL,
|
|
.fuse_opt_sec_debug_en = NULL,
|
|
.fuse_opt_priv_sec_en = NULL,
|
|
.read_vin_cal_fuse_rev = NULL,
|
|
.read_vin_cal_slope_intercept_fuse = NULL,
|
|
.read_vin_cal_gain_offset_fuse = NULL,
|
|
},
|
|
.acr = {
|
|
.acr_sw_init = NULL,
|
|
},
|
|
.chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
|
|
.get_litter_value = gp10b_get_litter_value,
|
|
};
|
|
|
|
int vgpu_gp10b_init_hal(struct gk20a *g)
|
|
{
|
|
struct gpu_ops *gops = &g->ops;
|
|
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
|
|
|
|
gops->ltc = vgpu_gp10b_ops.ltc;
|
|
gops->ce2 = vgpu_gp10b_ops.ce2;
|
|
gops->gr = vgpu_gp10b_ops.gr;
|
|
gops->gr.ctxsw_prog = vgpu_gp10b_ops.gr.ctxsw_prog;
|
|
gops->gr.config = vgpu_gp10b_ops.gr.config;
|
|
gops->fb = vgpu_gp10b_ops.fb;
|
|
gops->clock_gating = vgpu_gp10b_ops.clock_gating;
|
|
gops->fifo = vgpu_gp10b_ops.fifo;
|
|
gops->runlist = vgpu_gp10b_ops.runlist;
|
|
gops->channel = vgpu_gp10b_ops.channel;
|
|
gops->sync = vgpu_gp10b_ops.sync;
|
|
gops->netlist = vgpu_gp10b_ops.netlist;
|
|
#ifdef CONFIG_GK20A_CTXSW_TRACE
|
|
gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;
|
|
#endif
|
|
gops->mm = vgpu_gp10b_ops.mm;
|
|
gops->pramin = vgpu_gp10b_ops.pramin;
|
|
gops->therm = vgpu_gp10b_ops.therm;
|
|
gops->pmu = vgpu_gp10b_ops.pmu;
|
|
gops->clk_arb = vgpu_gp10b_ops.clk_arb;
|
|
gops->regops = vgpu_gp10b_ops.regops;
|
|
gops->mc = vgpu_gp10b_ops.mc;
|
|
gops->debug = vgpu_gp10b_ops.debug;
|
|
#ifdef NVGPU_DEBUGGER
|
|
gops->debugger = vgpu_gp10b_ops.debugger;
|
|
#endif
|
|
gops->perfbuf = vgpu_gp10b_ops.perfbuf;
|
|
gops->bus = vgpu_gp10b_ops.bus;
|
|
gops->ptimer = vgpu_gp10b_ops.ptimer;
|
|
#if defined(CONFIG_GK20A_CYCLE_STATS)
|
|
gops->css = vgpu_gp10b_ops.css;
|
|
#endif
|
|
gops->falcon = vgpu_gp10b_ops.falcon;
|
|
|
|
gops->priv_ring = vgpu_gp10b_ops.priv_ring;
|
|
|
|
gops->fuse = vgpu_gp10b_ops.fuse;
|
|
gops->acr = vgpu_gp10b_ops.acr;
|
|
|
|
/* Lone Functions */
|
|
gops->chip_init_gpu_characteristics =
|
|
vgpu_gp10b_ops.chip_init_gpu_characteristics;
|
|
gops->get_litter_value = vgpu_gp10b_ops.get_litter_value;
|
|
gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup;
|
|
|
|
g->pmu_lsf_pmu_wpr_init_done = 0;
|
|
|
|
if (priv->constants.can_set_clkrate) {
|
|
gops->clk.support_clk_freq_controller = true;
|
|
} else {
|
|
gops->clk.support_clk_freq_controller = false;
|
|
gops->clk_arb.get_arbiter_clk_domains = NULL;
|
|
}
|
|
|
|
g->name = "gp10b";
|
|
|
|
return 0;
|
|
}
|