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e70ba2af19
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed by brackets. This patch adds brackets to single line if/else/loop blocks in the vgpu directory. JIRA NVGPU-775 Change-Id: Ibdac461432867eab83c56c9fb55da70177ccce0f Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2011656 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/*
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* Virtualized GPU L2
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include "ltc_vgpu.h"
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int vgpu_determine_L2_size_bytes(struct gk20a *g)
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{
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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nvgpu_log_fn(g, " ");
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return priv->constants.l2_size;
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}
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int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
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{
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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u32 max_comptag_lines = 0;
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int err;
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nvgpu_log_fn(g, " ");
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gr->comptags_per_cacheline = priv->constants.comptags_per_cacheline;
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max_comptag_lines = priv->constants.comptag_lines;
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if (max_comptag_lines < 2) {
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return -ENXIO;
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}
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err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines);
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if (err) {
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return err;
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}
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gr->max_comptag_lines = max_comptag_lines;
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return 0;
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}
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void vgpu_ltc_init_fs_state(struct gk20a *g)
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{
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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struct gr_gk20a *gr = &g->gr;
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nvgpu_log_fn(g, " ");
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g->ltc_count = priv->constants.ltc_count;
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gr->cacheline_size = priv->constants.cacheline_size;
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gr->slices_per_ltc = priv->constants.slices_per_ltc;
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}
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