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Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
46 lines
2.1 KiB
C
46 lines
2.1 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef MC_GK20A_H
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#define MC_GK20A_H
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struct gk20a;
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void mc_gk20a_intr_enable(struct gk20a *g);
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void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
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bool is_stalling, u32 mask);
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void mc_gk20a_isr_stall(struct gk20a *g);
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u32 mc_gk20a_intr_stall(struct gk20a *g);
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void mc_gk20a_intr_stall_pause(struct gk20a *g);
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void mc_gk20a_intr_stall_resume(struct gk20a *g);
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u32 mc_gk20a_intr_nonstall(struct gk20a *g);
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u32 mc_gk20a_isr_nonstall(struct gk20a *g);
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void mc_gk20a_intr_nonstall_pause(struct gk20a *g);
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void mc_gk20a_intr_nonstall_resume(struct gk20a *g);
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void gk20a_mc_enable(struct gk20a *g, u32 units);
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void gk20a_mc_disable(struct gk20a *g, u32 units);
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void gk20a_mc_reset(struct gk20a *g, u32 units);
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u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
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bool mc_gk20a_is_intr1_pending(struct gk20a *g,
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enum nvgpu_unit unit, u32 mc_intr_1);
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void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops);
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#endif /* MC_GK20A_H */
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