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JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GPMUIFPERF_H_
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#define _GPMUIFPERF_H_
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#include "gpmuifvolt.h"
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#include "gpmuifperfvfe.h"
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/*
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* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId"
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* argument for communications between Kernel and PMU via the various generic
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* BOARDOBJGRP interfaces.
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*/
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#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00
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#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01
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#define NV_PMU_PERF_CMD_ID_RPC (0x00000002)
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#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003)
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#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004)
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struct nv_pmu_perf_cmd_set_object {
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u8 cmd_type;
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u8 pad[2];
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u8 object_type;
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struct nv_pmu_allocation object;
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};
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#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \
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(offsetof(struct nv_pmu_perf_cmd_set_object, object))
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/* RPC IDs */
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#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001)
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/*!
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* Command requesting execution of the perf RPC.
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*/
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struct nv_pmu_perf_cmd_rpc {
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u8 cmd_type;
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u8 pad[3];
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struct nv_pmu_allocation request;
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};
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#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \
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offsetof(struct nv_pmu_perf_cmd_rpc, request)
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/*!
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* Simply a union of all specific PERF commands. Forms the general packet
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* exchanged between the Kernel and PMU when sending and receiving PERF commands
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* (respectively).
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*/
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struct nv_pmu_perf_cmd {
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union {
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u8 cmd_type;
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struct nv_pmu_perf_cmd_set_object set_object;
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struct nv_pmu_boardobj_cmd_grp grp_set;
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struct nv_pmu_boardobj_cmd_grp grp_get_status;
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};
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};
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/*!
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* Defines the data structure used to invoke PMU perf RPCs. Same structure is
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* used to return the result of the RPC execution.
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*/
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struct nv_pmu_perf_rpc {
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u8 function;
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bool b_supported;
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bool b_success;
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flcn_status flcn_status;
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union {
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struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval;
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struct nv_pmu_perf_rpc_vfe_load vfe_load;
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} params;
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};
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/* PERF Message-type Definitions */
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#define NV_PMU_PERF_MSG_ID_RPC (0x00000003)
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#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004)
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#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006)
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/*!
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* Message carrying the result of the perf RPC execution.
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*/
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struct nv_pmu_perf_msg_rpc {
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u8 msg_type;
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u8 rsvd[3];
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struct nv_pmu_allocation response;
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};
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#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \
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(offsetof(struct nv_pmu_perf_msg_rpc, response))
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/*!
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* Simply a union of all specific PERF messages. Forms the general packet
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* exchanged between the Kernel and PMU when sending and receiving PERF messages
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* (respectively).
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*/
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struct nv_pmu_perf_msg {
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union {
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u8 msg_type;
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struct nv_pmu_perf_msg_rpc rpc;
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struct nv_pmu_boardobj_msg_grp grp_set;
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};
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};
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#endif /* _GPMUIFPERF_H_*/
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