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JIRA DNVGPU-184 Add structures and commands to send noise unware vmin value to pmu. This is needed to enable closed loop frequency controller support Change-Id: If2dfd5e76752a25765ba68821460b7fd2df23aed Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248208 (cherry picked from commit fcd73e0f0bca755ea745f62b52b9e641bc3aa1ae) Reviewed-on: http://git-master/r/1267434 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
329 lines
8.9 KiB
C
329 lines
8.9 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GPMUIFVOLT_H_
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#define _GPMUIFVOLT_H_
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#include "gk20a/gk20a.h"
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#include "gk20a/pmu_gk20a.h"
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#include "pmuif/gpmuifboardobj.h"
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#include "gk20a/pmu_common.h"
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#include "ctrl/ctrlvolt.h"
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#define NV_PMU_VOLT_VALUE_0V_IN_UV (0)
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/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */
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#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00
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#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01
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#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02
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struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_rail_boardobj_set {
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struct nv_pmu_boardobj super;
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u8 rel_limit_vfe_equ_idx;
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u8 alt_rel_limit_vfe_equ_idx;
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u8 ov_limit_vfe_equ_idx;
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u8 vmin_limit_vfe_equ_idx;
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u8 volt_margin_limit_vfe_equ_idx;
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u8 pwr_equ_idx;
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u8 volt_dev_idx_default;
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struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
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s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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};
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union nv_pmu_volt_volt_rail_boardobj_set_union {
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struct nv_pmu_boardobj board_obj;
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struct nv_pmu_volt_volt_rail_boardobj_set super;
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};
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NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail);
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/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */
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struct nv_pmu_volt_volt_device_boardobjgrp_set_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_device_boardobj_set {
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struct nv_pmu_boardobj super;
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u32 switch_delay_us;
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u32 voltage_min_uv;
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u32 voltage_max_uv;
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u32 volt_step_uv;
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};
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struct nv_pmu_volt_volt_device_vid_boardobj_set {
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struct nv_pmu_volt_volt_device_boardobj_set super;
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s32 voltage_base_uv;
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s32 voltage_offset_scale_uv;
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u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES];
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u8 vsel_mask;
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};
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struct nv_pmu_volt_volt_device_pwm_boardobj_set {
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struct nv_pmu_volt_volt_device_boardobj_set super;
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u32 raw_period;
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s32 voltage_base_uv;
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s32 voltage_offset_scale_uv;
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enum nv_pmu_pmgr_pwm_source pwm_source;
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};
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union nv_pmu_volt_volt_device_boardobj_set_union {
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struct nv_pmu_boardobj board_obj;
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struct nv_pmu_volt_volt_device_boardobj_set super;
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struct nv_pmu_volt_volt_device_vid_boardobj_set vid;
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struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm;
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};
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NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
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/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
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struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_policy_boardobj_set {
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struct nv_pmu_boardobj super;
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};
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struct nv_pmu_volt_volt_policy_sr_boardobj_set {
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struct nv_pmu_volt_volt_policy_boardobj_set super;
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u8 rail_idx;
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};
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set {
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struct nv_pmu_volt_volt_policy_boardobj_set super;
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u8 rail_idx_master;
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u8 rail_idx_slave;
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u8 delta_min_vfe_equ_idx;
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u8 delta_max_vfe_equ_idx;
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s32 offset_delta_min_uv;
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s32 offset_delta_max_uv;
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};
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struct nv_pmu_volt_volt_policy_srms_boardobj_set {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
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u16 inter_switch_delayus;
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};
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/* sr - > single_rail */
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struct nv_pmu_volt_volt_policy_srss_boardobj_set {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
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};
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union nv_pmu_volt_volt_policy_boardobj_set_union {
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struct nv_pmu_boardobj board_obj;
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struct nv_pmu_volt_volt_policy_boardobj_set super;
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struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail;
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail;
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struct nv_pmu_volt_volt_policy_srms_boardobj_set
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split_rail_m_s;
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struct nv_pmu_volt_volt_policy_srss_boardobj_set
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split_rail_s_s;
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};
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NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy);
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/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */
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struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_rail_boardobj_get_status {
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struct nv_pmu_boardobj_query super;
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u32 curr_volt_defaultu_v;
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u32 rel_limitu_v;
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u32 alt_rel_limitu_v;
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u32 ov_limitu_v;
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u32 max_limitu_v;
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u32 vmin_limitu_v;
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s32 volt_margin_limitu_v;
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u32 rsvd;
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};
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union nv_pmu_volt_volt_rail_boardobj_get_status_union {
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struct nv_pmu_boardobj_query board_obj;
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struct nv_pmu_volt_volt_rail_boardobj_get_status super;
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};
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NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail);
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/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */
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struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_device_boardobj_get_status {
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struct nv_pmu_boardobj_query super;
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};
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union nv_pmu_volt_volt_device_boardobj_get_status_union {
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struct nv_pmu_boardobj_query board_obj;
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struct nv_pmu_volt_volt_device_boardobj_get_status super;
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};
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NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device);
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/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */
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struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_policy_boardobj_get_status {
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struct nv_pmu_boardobj_query super;
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u32 offset_volt_requ_v;
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u32 offset_volt_curru_v;
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};
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struct nv_pmu_volt_volt_policy_sr_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_boardobj_get_status super;
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u32 curr_voltu_v;
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};
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_boardobj_get_status super;
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s32 delta_minu_v;
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s32 delta_maxu_v;
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s32 orig_delta_minu_v;
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s32 orig_delta_maxu_v;
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u32 curr_volt_masteru_v;
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u32 curr_volt_slaveu_v;
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bool b_violation;
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};
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/* srms -> split_rail_multi_step */
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struct nv_pmu_volt_volt_policy_srms_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
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};
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/* srss -> split_rail_single_step */
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struct nv_pmu_volt_volt_policy_srss_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
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};
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union nv_pmu_volt_volt_policy_boardobj_get_status_union {
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struct nv_pmu_boardobj_query board_obj;
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struct nv_pmu_volt_volt_policy_boardobj_get_status super;
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struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail;
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail;
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struct nv_pmu_volt_volt_policy_srms_boardobj_get_status
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split_rail_m_s;
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struct nv_pmu_volt_volt_policy_srss_boardobj_get_status
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split_rail_s_s;
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};
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NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy);
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struct nv_pmu_volt_policy_voltage_data {
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u8 policy_idx;
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struct ctrl_perf_volt_rail_list
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rail_list;
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};
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struct nv_pmu_volt_rail_get_voltage {
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u8 rail_idx;
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u32 voltage_uv;
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};
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struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin {
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u8 num_rails;
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struct ctrl_volt_volt_rail_list
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rail_list;
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};
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#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000)
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#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001)
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#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
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#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004)
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/*!
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* PMU VOLT RPC calls.
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*/
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#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000)
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#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002)
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#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003)
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struct nv_pmu_volt_cmd_rpc {
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u8 cmd_type;
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u8 pad[3];
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struct nv_pmu_allocation request;
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};
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#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \
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offsetof(struct nv_pmu_volt_cmd_rpc, request)
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struct nv_pmu_volt_cmd {
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union {
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u8 cmd_type;
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struct nv_pmu_boardobj_cmd_grp grp_set;
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struct nv_pmu_volt_cmd_rpc rpc;
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struct nv_pmu_boardobj_cmd_grp grp_get_status;
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};
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};
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struct nv_pmu_volt_rpc {
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u8 function;
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bool b_supported;
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bool b_success;
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flcn_status flcn_status;
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union {
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struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
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struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;
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struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin
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volt_rail_set_noise_unaware_vmin;
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} params;
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};
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/*!
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* VOLT MSG ID definitions
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*/
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#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000)
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#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001)
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#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
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/*!
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* Message carrying the result of the VOLT RPC execution.
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*/
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struct nv_pmu_volt_msg_rpc {
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u8 msg_type;
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u8 rsvd[3];
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struct nv_pmu_allocation response;
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};
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#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \
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offsetof(struct nv_pmu_volt_msg_rpc, response)
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struct nv_pmu_volt_msg {
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union {
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u8 msg_type;
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struct nv_pmu_boardobj_msg_grp grp_set;
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struct nv_pmu_volt_msg_rpc rpc;
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struct nv_pmu_boardobj_msg_grp grp_get_status;
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};
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};
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#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2)
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struct nv_pmu_volt_volt_rail_list {
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u8 num_rails;
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struct ctrl_perf_volt_rail_list_item
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rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
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};
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#endif /* _GPMUIFVOLT_H_*/
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