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421e64aad7
Update header path of gk20a.h in files present in common/ to <nvgpu/gk20a.h> Jira NVGPU-597 Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1832024 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
113 lines
3.5 KiB
C
113 lines
3.5 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "therm_gp106.h"
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#include "therm/thrmpmu.h"
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#include <nvgpu/hw/gp106/hw_therm_gp106.h>
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#include <nvgpu/utils.h>
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void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8)
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{
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*max_24_8 = (0x87 << 8);
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*min_24_8 = (((u32)-216) << 8);
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}
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int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
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{
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int err = 0;
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u32 readval;
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readval = gk20a_readl(g, therm_temp_sensor_tsense_r());
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if ((therm_temp_sensor_tsense_state_v(readval) &
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therm_temp_sensor_tsense_state_valid_v()) == 0U) {
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nvgpu_err(g,
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"Attempt to read temperature while sensor is OFF!");
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err = -EINVAL;
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} else if (therm_temp_sensor_tsense_state_v(readval) &
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therm_temp_sensor_tsense_state_shadow_v()) {
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nvgpu_err(g, "Reading temperature from SHADOWed sensor!");
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}
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// Convert from F9.5 -> F27.5 -> F24.8.
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readval &= therm_temp_sensor_tsense_fixed_point_m();
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*temp_f24_8 = readval;
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return err;
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}
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int gp106_elcg_init_idle_filters(struct gk20a *g)
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{
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u32 gate_ctrl, idle_filter;
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u32 engine_id;
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u32 active_engine_id = 0;
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struct fifo_gk20a *f = &g->fifo;
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nvgpu_log_fn(g, " ");
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for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
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active_engine_id = f->active_engines_list[engine_id];
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gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_exp_m(),
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therm_gate_ctrl_eng_idle_filt_exp_f(2));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_mant_m(),
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therm_gate_ctrl_eng_idle_filt_mant_f(1));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_before_m(),
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therm_gate_ctrl_eng_delay_before_f(0));
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gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
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}
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/* default fecs_idle_filter to 0 */
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idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
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idle_filter &= ~therm_fecs_idle_filter_value_m();
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gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
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/* default hubmmu_idle_filter to 0 */
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idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
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idle_filter &= ~therm_hubmmu_idle_filter_value_m();
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gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
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nvgpu_log_fn(g, "done");
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return 0;
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}
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u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp)
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{
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u32 err = 0;
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if (g->curr_warn_temp != curr_warn_temp) {
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g->curr_warn_temp = curr_warn_temp;
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err = therm_configure_therm_alert(g);
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}
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return err;
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}
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