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4e41a0b199
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for all 17.7 violations instandard C functions in OS/Posix interface. JIRA NVGPU-1036 Change-Id: I2da417edc992f16de24cdff536c0538f1fde8b61 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929901 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/vm.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/posix/posix-fault-injection.h>
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_Thread_local struct nvgpu_posix_fault_inj dma_fi = {
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.enabled = false,
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.counter = 0U,
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};
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struct nvgpu_posix_fault_inj *nvgpu_dma_alloc_get_fault_injection(void)
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{
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return &dma_fi;
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}
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/*
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* In userspace vidmem vs sysmem is just a difference in what is placed in the
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* aperture field.
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*/
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static int __nvgpu_do_dma_alloc(struct gk20a *g, unsigned long flags,
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size_t size, struct nvgpu_mem *mem,
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enum nvgpu_aperture ap)
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{
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void *memory;
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if (nvgpu_posix_fault_injection_handle_call(&dma_fi)) {
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return -ENOMEM;
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}
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memory = malloc(PAGE_ALIGN(size));
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if (memory == NULL)
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return -ENOMEM;
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mem->cpu_va = memory;
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mem->aperture = ap;
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mem->size = size;
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mem->aligned_size = PAGE_ALIGN(size);
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mem->gpu_va = 0ULL;
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mem->skip_wmb = true;
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mem->vidmem_alloc = NULL;
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mem->allocator = NULL;
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return 0;
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}
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bool nvgpu_iommuable(struct gk20a *g)
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{
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return false;
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}
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int nvgpu_dma_alloc_flags_sys(struct gk20a *g, unsigned long flags,
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size_t size, struct nvgpu_mem *mem)
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{
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/* note: fault injection handled in common function */
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return __nvgpu_do_dma_alloc(g, flags, size, mem, APERTURE_SYSMEM);
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}
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int nvgpu_dma_alloc_flags_vid_at(struct gk20a *g, unsigned long flags,
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size_t size, struct nvgpu_mem *mem, u64 at)
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{
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BUG();
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return 0;
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}
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void nvgpu_dma_free_sys(struct gk20a *g, struct nvgpu_mem *mem)
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{
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if (!(mem->mem_flags & NVGPU_MEM_FLAG_SHADOW_COPY))
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free(mem->cpu_va);
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(void) memset(mem, 0, sizeof(*mem));
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}
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void nvgpu_dma_free_vid(struct gk20a *g, struct nvgpu_mem *mem)
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{
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BUG();
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}
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