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4e41a0b199
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for all 17.7 violations instandard C functions in OS/Posix interface. JIRA NVGPU-1036 Change-Id: I2da417edc992f16de24cdff536c0538f1fde8b61 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929901 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/rwsem.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/posix/rwsem.h>
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void nvgpu_rwsem_init(struct nvgpu_rwsem *rwsem)
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{
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(void) memset(rwsem, 0, sizeof(*rwsem));
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nvgpu_spinlock_init(&rwsem->lock);
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}
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/*
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* Acquire.
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*/
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void nvgpu_rwsem_down_read(struct nvgpu_rwsem *rwsem)
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{
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while (true) {
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nvgpu_spinlock_acquire(&rwsem->lock);
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/*
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* If there's a writer try again.
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*/
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if (rwsem->writers < 0) {
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nvgpu_spinlock_release(&rwsem->lock);
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nvgpu_msleep(10);
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continue;
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}
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/*
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* Otherwise decrement the read counter and return.
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*/
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rwsem->readers -= 1;
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nvgpu_spinlock_release(&rwsem->lock);
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return;
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}
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}
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/*
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* Release.
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*/
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void nvgpu_rwsem_up_read(struct nvgpu_rwsem *rwsem)
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{
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nvgpu_spinlock_acquire(&rwsem->lock);
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rwsem->readers += 1;
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/*
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* Can't be any writers if there was a reader. Also can't be
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* a positive number of readers. The increments are always
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* downward so if we have a positive number then there is a
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* balancing bug.
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*/
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BUG_ON(rwsem->writers < 0);
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BUG_ON(rwsem->readers > 0);
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nvgpu_spinlock_release(&rwsem->lock);
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}
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void nvgpu_rwsem_down_write(struct nvgpu_rwsem *rwsem)
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{
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while (true) {
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nvgpu_spinlock_acquire(&rwsem->lock);
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/*
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* If there's a reader or a writer try again. Note: in this very
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* simple implementation it's possible for readers to
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* indefinitely starve writers.
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*/
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if (rwsem->writers < 0 || rwsem->readers < 0) {
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nvgpu_spinlock_release(&rwsem->lock);
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nvgpu_msleep(10);
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continue;
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}
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rwsem->writers -= 1;
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nvgpu_spinlock_release(&rwsem->lock);
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return;
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}
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}
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void nvgpu_rwsem_up_write(struct nvgpu_rwsem *rwsem)
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{
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nvgpu_spinlock_acquire(&rwsem->lock);
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rwsem->writers += 1;
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/*
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* Writers can't be positive: that would be an unbalanced free. Readers
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* must be zero - otherwise this writer should never have had access!
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*/
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BUG_ON(rwsem->writers > 0);
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BUG_ON(rwsem->readers != 0);
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nvgpu_spinlock_release(&rwsem->lock);
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}
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