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89660dbd62
MISRA rule 14.4 doesn't allow the usage of integer types as booleans in the controlling expression of an if statement or an iteration statement. Fix violations where the result of a bitwise operation is used as a boolean in the controlling expression of if and loop statements. JIRA NVGPU-1020 Change-Id: If910150072c3dd67c31fe9819c3a9e738fd3c1c6 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1932389 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
/*
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* Volta GPU series Copy Engine.
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include "nvgpu/log.h"
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#include "nvgpu/bitops.h"
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#include <nvgpu/gk20a.h>
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#include "gp10b/ce_gp10b.h"
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#include "ce_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_ce_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
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u32 gv11b_ce_get_num_pce(struct gk20a *g)
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{
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/* register contains a bitmask indicating which physical copy
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* engines are present (and not floorswept).
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*/
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u32 num_pce;
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u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r());
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num_pce = hweight32(ce_pce_map);
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nvgpu_log_info(g, "num PCE: %d", num_pce);
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return num_pce;
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}
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void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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u32 clear_intr = 0;
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nvgpu_log(g, gpu_dbg_intr, "ce isr 0x%08x 0x%08x", ce_intr, inst_id);
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/* An INVALID_CONFIG interrupt will be generated if a floorswept
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* PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG
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* registers. This is a fatal error and the LCE will have to be
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* reset to get back to a working state.
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*/
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if ((ce_intr & ce_intr_status_invalid_config_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr,
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"ce: inst %d: invalid config", inst_id);
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clear_intr |= ce_intr_status_invalid_config_reset_f();
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}
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/* A MTHD_BUFFER_FAULT interrupt will be triggered if any access
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* to a method buffer during context load or save encounters a fault.
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* This is a fatal interrupt and will require at least the LCE to be
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* reset before operations can start again, if not the entire GPU.
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*/
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if ((ce_intr & ce_intr_status_mthd_buffer_fault_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr,
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"ce: inst %d: mthd buffer fault", inst_id);
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clear_intr |= ce_intr_status_mthd_buffer_fault_reset_f();
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}
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gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
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gp10b_ce_isr(g, inst_id, pri_base);
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}
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u32 gv11b_ce_get_num_lce(struct gk20a *g)
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{
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u32 reg_val, num_lce;
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reg_val = gk20a_readl(g, top_num_ces_r());
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num_lce = top_num_ces_value_v(reg_val);
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nvgpu_log_info(g, "num LCE: %d", num_lce);
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return num_lce;
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}
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void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g)
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{
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u32 reg_val, num_lce, lce, clear_intr;
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num_lce = gv11b_ce_get_num_lce(g);
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for (lce = 0; lce < num_lce; lce++) {
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reg_val = gk20a_readl(g, ce_intr_status_r(lce));
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if ((reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr,
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"ce: lce %d: mthd buffer fault", lce);
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clear_intr = ce_intr_status_mthd_buffer_fault_reset_f();
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gk20a_writel(g, ce_intr_status_r(lce), clear_intr);
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}
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}
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}
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