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ae96316a85
Currently ACR bootstrap functions are mixed with common ACR public functions file, so need to separate it out JIRA NVGPU-2911 Change-Id: I433514f1924a13e206d80d756b78056dbb2e4841 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2033812 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/acr/nvgpu_acr.h>
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#include <nvgpu/gk20a.h>
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#include "acr_gm20b.h"
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#include "acr_gp10b.h"
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#include "acr_gv11b.h"
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#include "acr_gv100.h"
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#include "acr_tu104.h"
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/* Both size and address of WPR need to be 128K-aligned */
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#define DGPU_WPR_SIZE 0x200000U
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int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size,
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struct nvgpu_mem *mem)
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{
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return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_PHYSICALLY_ADDRESSED,
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size, mem);
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}
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int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size,
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struct nvgpu_mem *mem)
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{
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struct wpr_carveout_info wpr_inf;
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int err;
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if (mem->size != 0ULL) {
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return 0;
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}
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g->acr.get_wpr_info(g, &wpr_inf);
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/*
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* Even though this mem_desc wouldn't be used, the wpr region needs to
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* be reserved in the allocator.
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*/
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err = nvgpu_dma_alloc_vid_at(g, wpr_inf.size,
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&g->acr.wpr_dummy, wpr_inf.wpr_base);
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if (err != 0) {
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return err;
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}
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return nvgpu_dma_alloc_vid_at(g, wpr_inf.size, mem,
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wpr_inf.nonwpr_base);
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}
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void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf)
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{
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g->ops.fb.read_wpr_info(g, inf);
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}
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void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf)
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{
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inf->wpr_base = g->mm.vidmem.bootstrap_base;
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inf->nonwpr_base = inf->wpr_base + DGPU_WPR_SIZE;
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inf->size = DGPU_WPR_SIZE;
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}
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int nvgpu_acr_construct_execute(struct gk20a *g){
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int err = 0;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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goto done;
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}
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err = g->acr.prepare_ucode_blob(g);
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if (err != 0) {
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nvgpu_err(g, "ACR ucode blob prepare failed");
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goto done;
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}
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err = g->acr.bootstrap_hs_acr(g, &g->acr, &g->acr.acr);
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if (err != 0) {
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nvgpu_err(g, "ACR bootstrap failed");
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goto done;
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}
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done:
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return err;
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}
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void nvgpu_acr_init(struct gk20a *g)
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{
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u32 ver = g->params.gpu_arch + g->params.gpu_impl;
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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return;
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}
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switch (ver) {
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case GK20A_GPUID_GM20B:
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case GK20A_GPUID_GM20B_B:
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nvgpu_gm20b_acr_sw_init(g, &g->acr);
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break;
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case NVGPU_GPUID_GP10B:
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nvgpu_gp10b_acr_sw_init(g, &g->acr);
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break;
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case NVGPU_GPUID_GV11B:
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nvgpu_gv11b_acr_sw_init(g, &g->acr);
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break;
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case NVGPU_GPUID_GV100:
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nvgpu_gv100_acr_sw_init(g, &g->acr);
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break;
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case NVGPU_GPUID_TU104:
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nvgpu_tu104_acr_sw_init(g, &g->acr);
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break;
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default:
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nvgpu_err(g, "no support for GPUID %x", ver);
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break;
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}
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}
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