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0a762889c6
engine queue head and tail methods were retrieved from falcon structure. engine queue initialization can get these methods directly from hal through params. Also eliminate struct nvgpu_falcon dereference in engine queue sources to remove inclusion of falcon_priv.h. JIRA NVGPU-1994 Change-Id: Idbebd5049cfd14eb3fe0e27b2bef8436cc61e101 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2016290 GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
123 lines
4.2 KiB
C
123 lines
4.2 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FALCON_PRIV_H
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#define NVGPU_FALCON_PRIV_H
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#include <nvgpu/lock.h>
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#include <nvgpu/types.h>
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/* Falcon Register index */
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#define FALCON_REG_R0 (0U)
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#define FALCON_REG_R1 (1U)
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#define FALCON_REG_R2 (2U)
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#define FALCON_REG_R3 (3U)
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#define FALCON_REG_R4 (4U)
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#define FALCON_REG_R5 (5U)
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#define FALCON_REG_R6 (6U)
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#define FALCON_REG_R7 (7U)
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#define FALCON_REG_R8 (8U)
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#define FALCON_REG_R9 (9U)
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#define FALCON_REG_R10 (10U)
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#define FALCON_REG_R11 (11U)
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#define FALCON_REG_R12 (12U)
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#define FALCON_REG_R13 (13U)
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#define FALCON_REG_R14 (14U)
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#define FALCON_REG_R15 (15U)
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#define FALCON_REG_IV0 (16U)
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#define FALCON_REG_IV1 (17U)
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#define FALCON_REG_UNDEFINED (18U)
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#define FALCON_REG_EV (19U)
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#define FALCON_REG_SP (20U)
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#define FALCON_REG_PC (21U)
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#define FALCON_REG_IMB (22U)
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#define FALCON_REG_DMB (23U)
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#define FALCON_REG_CSW (24U)
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#define FALCON_REG_CCR (25U)
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#define FALCON_REG_SEC (26U)
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#define FALCON_REG_CTX (27U)
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#define FALCON_REG_EXCI (28U)
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#define FALCON_REG_RSVD0 (29U)
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#define FALCON_REG_RSVD1 (30U)
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#define FALCON_REG_RSVD2 (31U)
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#define FALCON_REG_SIZE (32U)
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struct gk20a;
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struct nvgpu_falcon;
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struct nvgpu_falcon_bl_info;
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enum falcon_mem_type {
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MEM_DMEM = 0,
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MEM_IMEM
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};
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/* ops which are falcon engine specific */
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struct nvgpu_falcon_engine_dependency_ops {
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int (*reset_eng)(struct gk20a *g);
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int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
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u32 size, u8 port);
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int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
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u32 size, u8 port);
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};
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struct nvgpu_falcon_ops {
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void (*reset)(struct nvgpu_falcon *flcn);
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void (*set_irq)(struct nvgpu_falcon *flcn, bool enable,
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u32 intr_mask, u32 intr_dest);
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bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);
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bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
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bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
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bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn);
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int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
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u32 size, u8 port);
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int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
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u32 size, u8 port);
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int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
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u32 size, u8 port);
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int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
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u32 size, u8 port, bool sec, u32 tag);
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u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index);
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void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index,
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u32 data);
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int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
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void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
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int (*bl_bootstrap)(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_bl_info *bl_info);
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void (*get_falcon_ctls)(struct nvgpu_falcon *flcn, u32 *sctl,
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u32 *cpuctl);
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u32 (*get_mem_size)(struct nvgpu_falcon *flcn,
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enum falcon_mem_type mem_type);
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};
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struct nvgpu_falcon {
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struct gk20a *g;
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u32 flcn_id;
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u32 flcn_base;
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bool is_falcon_supported;
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bool is_interrupt_enabled;
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struct nvgpu_mutex copy_lock;
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struct nvgpu_falcon_ops flcn_ops;
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struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
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};
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#endif /* NVGPU_FALCON_PRIV_H */
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