mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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6a6c2ec0b0
This patch does the following. 1. Append public functions with nvgpu. 2. Move public functions & structure to include/pmu/clk. 3. Remove inclusion of HW header files in common. 4. Move FREQ_STEP_SIZE_MHZ to clk_prog.h as it is used there. 5. Fix 16.3 and 11.3 Misra Violations. Jira NVGPU-1965 Change-Id: I268d257d6de9c986e456a666cf6d633fe10fc440 Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2024992 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
130 lines
4.1 KiB
C
130 lines
4.1 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_PROG_H
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#define NVGPU_CLK_PROG_H
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#include <nvgpu/pmuif/ctrlclk.h>
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#include <nvgpu/pmuif/ctrlboardobj.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/boardobjgrp_e255.h>
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#include <nvgpu/boardobjgrpmask.h>
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struct clk_prog_1x_master;
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#define FREQ_STEP_SIZE_MHZ 15U
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typedef int vf_flatten(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u8 clk_domain_idx, u16 *pfreqmaxlastmhz);
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typedef int vf_lookup(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u8 *slave_clk_domain_idx, u16 *pclkmhz,
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u32 *pvoltuv, u8 rail);
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typedef int get_slaveclk(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u8 slave_clk_domain_idx, u16 *pclkmhz,
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u16 masterclkmhz);
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typedef int get_fpoints(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
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struct clk_prog_1x_master *p1xmaster,
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u32 *pfpointscount,
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u16 **ppfreqpointsinmhz, u8 rail);
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struct clk_prog {
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struct boardobj super;
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};
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struct clk_prog_1x {
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struct clk_prog super;
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u8 source;
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u16 freq_max_mhz;
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union ctrl_clk_clk_prog_1x_source_data source_data;
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};
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struct clk_prog_1x_master {
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struct clk_prog_1x super;
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bool b_o_c_o_v_enabled;
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struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_entries;
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struct ctrl_clk_clk_delta deltas;
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union ctrl_clk_clk_prog_1x_master_source_data source_data;
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vf_flatten *vfflatten;
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vf_lookup *vflookup;
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get_fpoints *getfpoints;
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get_slaveclk *getslaveclk;
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};
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struct clk_prog_1x_master_ratio {
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struct clk_prog_1x_master super;
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struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *p_slave_entries;
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};
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struct clk_prog_1x_master_table {
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struct clk_prog_1x_master super;
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struct ctrl_clk_clk_prog_1x_master_table_slave_entry *p_slave_entries;
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};
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struct clk_prog_3x_master {
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bool b_o_c_o_v_enabled;
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struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_entries;
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struct ctrl_clk_clk_delta deltas;
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union ctrl_clk_clk_prog_1x_master_source_data source_data;
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vf_flatten *vfflatten;
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vf_lookup *vflookup;
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get_fpoints *getfpoints;
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get_slaveclk *getslaveclk;
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};
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struct clk_prog_3x_master_ratio {
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struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *p_slave_entries;
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};
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struct clk_prog_3x_master_table {
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struct ctrl_clk_clk_prog_1x_master_table_slave_entry *p_slave_entries;
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};
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struct clk_prog_35_master {
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struct clk_prog_1x super;
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struct clk_prog_3x_master master;
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struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail
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*p_voltrail_sec_vf_entries;
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};
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struct clk_prog_35_master_ratio {
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struct clk_prog_35_master super;
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struct clk_prog_3x_master_ratio ratio;
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};
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struct clk_prog_35_master_table {
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struct clk_prog_35_master super;
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struct clk_prog_3x_master_table table;
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};
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#define CLK_CLK_PROG_GET(pclk, idx) \
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((struct clk_prog *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&pclk->clk_progobjs.super.super, (u8)(idx)))
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#endif /* NVGPU_CLK_PROG_H */
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