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bfc3c57afb
Fix MISRA Rule 10.3 violations in common/pmu/perf for assigning objects of different size or essential type. JIRA NVGPU-1008 Change-Id: I7fa7f981ba80c2d6951821ed3c847a814fc8b3b6 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2027654 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
128 lines
3.6 KiB
C
128 lines
3.6 KiB
C
/*
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* GV100 PERF
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*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu/clk/clk.h>
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#include <nvgpu/pmu/perf.h>
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#include "perf_gv100.h"
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#include "pmu_perf.h"
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static int pmu_set_boot_clk_runcb_fn(void *arg)
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{
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struct gk20a *g = (struct gk20a *)arg;
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_perf_load rpc;
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struct perf_pmupstate *perf_pmu = g->perf_pmu;
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struct nvgpu_vfe_invalidate *vfe_init = &perf_pmu->vfe_init;
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int status = 0;
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nvgpu_log_fn(g, "thread start");
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while (true) {
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NVGPU_COND_WAIT_INTERRUPTIBLE(&vfe_init->wq,
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(vfe_init->state_change ||
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nvgpu_thread_should_stop(&vfe_init->state_task)), 0U);
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if (nvgpu_thread_should_stop(&vfe_init->state_task)) {
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break;
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}
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vfe_init->state_change = false;
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(void) memset(&rpc, 0,
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sizeof(struct nv_pmu_rpc_struct_perf_load));
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PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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status = nvgpu_clk_set_fll_clk_gv10x(g);
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}
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return 0;
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}
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static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
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{
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struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmumsg;
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struct perf_pmupstate *perf_pmu = g->perf_pmu;
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nvgpu_log_fn(g, " ");
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switch (msg->msg_type) {
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case NV_PMU_PERF_MSG_ID_VFE_CALLBACK:
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perf_pmu->vfe_init.state_change = true;
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nvgpu_cond_signal(&perf_pmu->vfe_init.wq);
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break;
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default:
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WARN_ON(true);
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break;
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}
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return 0;
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}
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static int perf_pmu_init_vfe_perf_event(struct gk20a *g)
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{
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struct perf_pmupstate *perf_pmu = g->perf_pmu;
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char thread_name[64];
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int err = 0;
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nvgpu_log_fn(g, " ");
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nvgpu_cond_init(&perf_pmu->vfe_init.wq);
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(void) snprintf(thread_name, sizeof(thread_name),
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"nvgpu_vfe_invalidate_init_%s", g->name);
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err = nvgpu_thread_create(&perf_pmu->vfe_init.state_task, g,
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pmu_set_boot_clk_runcb_fn, thread_name);
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if (err != 0) {
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nvgpu_err(g, "failed to start nvgpu_vfe_invalidate_init thread");
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}
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return err;
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}
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int gv100_perf_pmu_vfe_load(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_perf_load rpc;
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int status = 0;
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(void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load));
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PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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perf_pmu_init_vfe_perf_event(g);
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/*register call back for future VFE updates*/
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g->ops.pmu_perf.handle_pmu_perf_event = gv100_pmu_handle_perf_event;
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return status;
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}
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